Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-25
15.6.4
QSPI Operation
The QSPI uses a dedicated 160-byte block of static RAM accessible by both the QSPI and the CPU to
perform queued operations. The RAM is divided into three segments: 32 command control bytes, 64
transmit data bytes, and 64 receive data bytes.
Once the CPU has set up a queue of QSPI commands, written the transmit data segment with information
to be sent, and enabled the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of
the commands in its queue, sets a flag indicating completion, and then either interrupts the CPU or waits
for CPU intervention.
QSPI RAM is organized so that one byte of command data, one word of transmit data, and one word of
receive data correspond to each queue entry, 0x0 to 0x2F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing
transmit data into transmit RAM, then enabling the QSPI. The QSPI executes the queued commands, sets
a completion flag (SPIF), and then either interrupts the CPU or waits for intervention.
There are four queue pointers. The CPU can access three of them through fields in QSPI registers. The
new queue pointer (NEWQP), contained in SPCR2, points to the first command in the queue. An internal
queue pointer points to the command currently being executed. The completed queue pointer (CPTQP),
contained in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in
SPCR2, points to the final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal operation, the command
pointed to by the internal pointer is executed, the value in the internal pointer is copied into CPTQP, the
internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer
address unless the NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
Table 15-20. QSPI Pin Functions
Pin Names
Mnemonic
Mode
Function
Master in slave out
MISO
Master
Slave
Serial data input to QSPI
Serial data output from QSPI
Master out slave in
MOSI
Master
Slave
Serial data output from QSPI
Serial data input to QSPI
Serial clock
SCK
1
1
All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI is operating.
SCK can only be used for general-purpose I/O if the QSPI is disabled.
Master
Slave
Clock output from QSPI clock
Input to QSPI
Peripheral chip selects
PCS[1:3]
Master
Outputs select peripheral(s)
Peripheral chip select
2
Slave select
3
2
An output (PCS0) when the QSPI is in master mode.
3
An input (SS) when the QSPI is in slave mode.
PCS0 /
SS
Master
Slave
Output selects peripheral(s)
Input selects the QSPI
Slave select
4
4
An input (SS) when the QSPI is in master mode; useful in multimaster systems.
SS
Master
May cause mode fault
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
