Modular Input/Output Subsystem (MIOS14)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-49
•
An output flip-flop with output buffer and polarity control
•
An input/output signal with data direction control
•
An 8-bit prescaler and clock selection logic
•
A 16-bit down-counter (MPWMCNTR)
•
A register to hold the next period values (MPWMPERR)
•
Two registers to hold the current and next pulse width values (MPWMPULR)
•
A less-than or equal comparator
•
A status and control register (MPWMSCR)
17.10.3.1 Clock Selection
The MPWMSM contains an 8-bit prescaler clocked by the output signal from the MIOS14 counter
prescaler submodule (f
SYS
/2 to f
SYS
/16). The MPWMSM clock selector allows the choice, by software,
of one of 256 divide ratios which give to the MPWMSM a large choice of frequencies available for the
down-counter. The MPWMSM down-counter is thus capable of counting with a clock frequency ranging
from f
SYS
/2 to f
SYS
/4096.
Switching the MPWMSM from disable to enable will reload the value of MPWMSCR[CP] into the 8-bit
prescaler counter.
17.10.3.2 Counter
A 16-bit down-counter in the MPWMSM provides the time reference for the output signal. The counter is
software writable. When writing to the counter (i.e., at the MPWMCNTR address), it also writes to the
MPWMPERR register. When in transparent mode (TRSP = 1), writing to the MPWMPERR will also write
to the counter. The down-counter is readable at anytime. The value loaded in the down-counter
corresponds to the period of the output signal.
When the MPWMSM is enabled, the counter begins counting. As long as it is enabled, the counter counts
down freely. The counter counts at the rate established by the prescaler. When the count down reaches
0x0001, the load operation is executed and the value in the MPWMPERR register is loaded in the
MPWMCNTR register, (i.e., the counter). Then the counter restarts to count down from that value.
17.10.3.3 Period Register
The period section is composed of a 16-bit data register (MPWMPERR). The software establishes the
period of the output signal in register MPWMPERR.
When the MPWMSM is running in transparent mode, the period value in register MPWMPERR is
immediately transferred to the counter on a write to the MPWMPERR.
When the MPWMSM is running in double-buffered mode, the period value in register MPWMPERR can
be changed at any time without affecting the current period of the output signal. The new value of
MPWMPERR will be transferred to the counter only when the counter reaches the value of 0x0001 and
generates a load signal.
Period values of 0x0000, 0x0001, and 0x0002 are MPWMSM special cases:
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
