Modular Input/Output Subsystem (MIOS14)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-59
.
Table 17-29. MPWMSCR Bit Descriptions
Bits
Name
Description
0
PIN
Pin input status bit — The PIN bit reflects the state present on the MPWMSM signal. The
software can thus monitor the pin state.
The PIN bit is a read-only bit. Writing to the PIN bit has no effect.
1
DDR
Data direction register — The DDR bit indicates the direction for the signal when the PWM
function is not used (disable mode).
0 signal is in input.
1 signal is in output.
The DDR bit is cleared by reset.
lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
2
FREN
Freeze enable bit — This active high read/write control bit enables the MPWMSM to recognize
the freeze signal on the MIOB.
0 MPWMSM not frozen even if the MIOB freeze line is active.
1 MPWMSM frozen if the MIOB freeze line is active.
The FREN is cleared by reset.
3
TRSP
Transparent mode — The TRSP bit indicates that the MPWMSM is in transparent mode. In
transparent mode, when the software writes to either the MPWMPERR or MPWMPULR1 register
the value written is immediately transferred to the counter or register MPWMPULR2 respectively.
0 Double-buffered mode.
1 Transparent mode.
The TRSP bit is cleared by reset.
4
POL
Output polarity control bit — The POL bit works in conjunction with the EN bit and controls
whether the MPWMSM drives the signal with the direct or the inverted value of the output flip-flop.
lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
5
EN
Enable PWM signal generation — The EN bit defines whether the MPWMSM generates a PWM
signal or is used as an I/O channel:
0 PWM generation disabled (signal can be used as I/O).
1 PWM generation enabled (the signal is in output mode).
Each time the submodule is enabled, the value of CP is loaded into the prescaler.
The EN bit is cleared by reset.
6:7
—
Reserved
8:15
CP
Clock prescaler — This 8-bit read/write data register stores the modulus value for loading into
the built-in 8-bit clock prescaler. The value loaded defines the divide ratio for the signal that clocks
the MPWMSM. The new value is loaded into the prescaler counter on the prescaler counter
overflow, or upon the EN bit of the MPWMSCR being set.
gives the clock divide ratio according to the value of CP.
Table 17-30. PWMSM Output Signal Polarity Selection
Control Bits
Signal
Direction
Signal State
Periodic Edge
Variable Edge
Optional
InterruptIon
POL
EN
DDR
0
0
0
Input
INPUT
—
—
—
0
0
1
Output
Always Low
—
—
—
0
1
X
Output
High Pulse
Falling Edge
Rising Edge
Falling Edge
1
0
0
Input
INPUT
—
—
—
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
