Peripheral Pin Multiplexing (PPM) Module
MPC561/MPC563 Reference Manual, Rev. 1.2
18-12
Freescale Semiconductor
18.4.2
PPM Control Register (PPMPCR)
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field SAMP[0:2]
OP_16_8 ENRX ENTX
SPI
STR
CI
CP
CM
RESERVED
SRESET
0000_0000_0000_0000
Addr
0x30 5C04
Figure 18-9. PPM Control Register (PPMPCR)
Table 18-3. PPMPCR Bit Descriptions
Bits
Name
Description
0:2
SAMP[0:2]
The Sample rate is the rate at which the data registers are sampled, with respect to the
frequency of TCLK. For transmit, SAMP[0:2] is the rate at which data from the TX_DATA
register is sampled. For receive, SAMP[0:2] is the rate at which data is sampled from
RX_DATA.
Refer to
for SAMP[0:2] settings.
3
OP_16_8
This bit describes how the 16 data bits will be transmitted and received. Both transmit and
receive are effected by this bit setting.
0 16 TCLK Cycles per word. All 16 bits of TX_DATA[0:15] will transmit on PPM_TX0. All 16
bits of RX_SHIFTER[0:15] are received from PPM_RX0.
1 8 TCLK Cycles per word. TX_DATA[0:7] will transmit on PPM_TX1, TX_DATA[8:15] will
transmit on PPM_TX_0. RX_SHIFTER[0:7] are received from PPM_RX1,
RX_SHIFTER[8:15] are received from PPM_RX0.
4
ENRX
1
PPM Receive (RX) data enable.
0 RX Disabled
1 RX Enabled
5
ENTX
2
PPM Transmit (TX) data enable.
0 TX Disabled
1 TX Enabled
6
SPI
SPI mode enable.
0 TDM mode enabled
1 SPI mode enabled
7
STR
Start-Transmit-Receive bit. When this bit is set and SPI mode is enabled, the PPM module
will start to transmit and/or receive one frame of data. The STR bit will then be cleared
automatically by the PPM. Refer to
0 PPM has completed transmitting and/or receiving one data frame.
1 PPM will transmit and/or receive one data frame.
8
CI
Clock Invert. This bit defines the polarity of TCLK clock in both SPI and TDM modes.
0 Normal clock polarity – active high clocks selected
1 Inverted clock – active low clocks selected
9
CP
Clock Phase. This bit selects one of two fundamentally different transfer formats. Refer to
figures
.
0 Valid data can be latched on the transition of TCLK from inactive phase to active phase.
1 Valid data can be latched on the transition of TCLK from active phase to inactive phase.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
