Time Processor Unit 3
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
19-5
or with custom functions. Refer to Freescale Programming Note,
Using the TPU Function Library and
TPU Emulation Mode
(TPUPN00/D)
for information about developing custom functions and accessing
the TPU function library. Refer to
General TPU C Functions for the MPC500 Family
(AN2360/D) for
more information about TPU functions in general and the T
PU Literature Package
(TPULITPAK/D) for
more information about specific functions.
19.3.7
TPU3 Interrupts
Each of the TPU3 channels can generate an interrupt service request. Interrupts for each channel must be
enabled by writing to the appropriate control bit in the channel interrupt enable register (CIER). The
channel interrupt status register (CISR) contains one interrupt status flag per channel. Time functions set
the flags. Setting a flag bit causes the TPU3 to make an interrupt service request if the corresponding
channel interrupt enable bit is set.
The TPU3 can generate one of 32 possible interrupt request levels on the IMB3. The value driven onto
IRQ[7:0] represents the interrupt level programmed in the IRL field of the TPU interrupt configuration
register (TICR). Under the control of the ILBS bits in the ICR, each interrupt request level is driven during
one of four different time-multiplexed time slots, with eight levels communicated per time slot. No
hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an
interrupt at the same level, the system software must assign a priority to each source requesting at that
level.
displays the interrupt level scheme.
Figure 19-2. TPU3 Interrupt Levels
19.3.8
Prescaler Control for TCR1
Timer count register 1 (TCR1) is clocked from the output of a prescaler. The following fields control
TCR1:
•
The PSCK and TCR1P fields in TPUMCR
•
The DIV2 field in TPUMCR2
•
The EPSCKE and EPSCK fields in TPUMCR3.
The rate at which TCR1 is incremented is determined as follows:
•
The user selects either the standard prescaler (by clearing the enhanced prescaler enable bit,
EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting EPSCKE).
— If the standard prescaler is selected (EPSCKE = 0), then the PSCK bit determines whether the
standard prescaler divides the system clock input by 32 (PSCK = 0) or 4 (PSCK = 1)
IMB3 CLOCK
ILBS[1:0]
IMB3
IRQ
[7:0]
IRQ
7:0
00
01
11
10
IRQ
15:8
IRQ
23:16
IRQ
31:24
IRQ
7:0
00
01
11
10
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
