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Freescale Semiconductor MPC561, Reference Manual

The Freescale Semiconductor MPC561 is a powerful microcontroller perfect for embedded systems. For a complete understanding of its capabilities, download the comprehensive Reference Manual for free from 88.208.23.73:8080. This manual provides detailed instructions and information on how to maximize the potential of your MPC561.

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CDR3 Flash (UC3F) EEPROM

MPC561/MPC563 Reference Manual, Rev. 1.2

21-6

Freescale Semiconductor

 

Table 21-3. UC3FMCR Bit Descriptions

Bits

Name

Description

0

STOP

Array stop control. Writes to the STOP bit have no effect while in program or erase operation 
(SES = 1). The STOP bit is always readable whenever the registers are enabled. 
When STOP = 1, the reset state of STOP is 1 and the UC3F array is disabled; internal circuits are 
switched into a low power state. The STOP bit may be used to implement low power standby 
modes or power management schemes. The UC3FMCR remains readable and writable when 
STOP = 1 so that the STOP bit may be deasserted.  Attempts to program or erase the array while 
STOP = 1 have no effect. SES cannot be set to 1 when STOP = 1. 
When STOP = 0, the reset state of STOP is 0 and the UC3F array is enabled for accesses. All 
registers that were disabled with STOP = 1 are now enabled. A STOP recovery time of 1 

µ

s is 

required for biases in the UC3F array to reach their appropriate states to resume normal operation. 
Operations to the UC3F array should be delayed for at least 1

µ

s after clearing the STOP bit.

0 = UC3F array is enabled 
1 = UC3F array is disabled (low-power mode)

1

LOCK

1

 

Lock control. The default reset state of LOCK is 1. This enables writing of all fields in the Flash 
registers. 
Once the LOCK bit has been asserted (LOCK = 0) in normal operating mode, the write-lock can 
only be disabled again by a reset. When the device is in background debug mode and CSC = 0, 
the LOCK bit may be written from a 0 to a 1. 
When the LOCK control bit is cleared to 0, the write-locked register bits: FIC, SUPV, SBSUPV[0:1], 
DATA, SBDATA, PROTECT, SBPROTECT, and SBEN[0:1] are locked. Writes to these bits while 
LOCK = 0 will have no effect.
LOCK can be written to 0 once after reset when UC3FCTL[CSC] = 0 to allow protection of the 
write-locked register bits after initialization.

WARNING: 

If the lock protection mechanism is enabled (LOCK = 0) before PROTECT and 
SBPROTECT are cleared, the device must use background debug mode to 
program or erase the UC3F EEPROM.

2

—

Reserved

3

FIC

Force information censorship. The default reset state of FIC is normal censorship operation 
(FIC = 0). The FIC bit is write protected by the LOCK bit and the UC3FCTL[CSC] bit. Writes will 
have no effect if LOCK = 0 or CSC = 1. Once FIC is set (FIC = 1), it cannot be cleared except by 
a reset. The FIC bit can be read whenever the registers are enabled.
The FIC bit is a censorship emulation mode used to aid in the development of custom techniques 
for controlling the ACCESS bit without setting CENSOR[0:1] to the information censorship state. 
Using FIC to force information censorship allows testing of the hardware and software for setting 
ACCESS without setting CENSOR[0:1] = 11 and risk permanently setting the device into an 
unusable information censorship state.
0 = normal uc3f censorship operation
1 = forces the uc3f into information censorship mode

4

SIE

Shadow information enable. The default reset state of SIE is 0. The SIE bit is write protected in 
program operation (SES = 1 and PE = 0). The SIE bit can be read whenever the registers are 
enabled.
When SIE = 1, normal array accesses are disabled, and the two shadow information rows are 
enabled. Array accesses are directed to the shadow row while SIE = 1. When an array location is 
read in this mode, only the lower 6 address bits are used to select which 64 bytes of the 512-byte 
shadow row are read. The upper address bits are not used for shadow row decoding. The read 
page buffer address monitor is reset whenever SIE is modified making the next UC3F array access 
an off page access.
0 = normal array access
1 = disables normal array access and selects the shadow information rows

Summary of Contents for MPC561

Page 1: ...MPC561 MPC563 Reference Manual Additional Devices Supported MPC562 MPC564 MPC561RM REV 1 2 08 2005...

Page 2: ...ny liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical p...

Page 3: ...Unit 1 5 1 3 1 5 Memory Controller 1 5 1 3 1 6 512 Kbytes of CDR3 Flash EEPROM Memory UC3F MPC563 MPC564 Only 1 5 1 3 1 7 32 Kbyte Static RAM CALRAM 1 6 1 3 1 8 General Purpose I O Support GPIO 1 6 1...

Page 4: ...ty Configuration Out of Reset 2 31 2 6 2 Signal State During Reset 2 31 2 6 3 Power On Reset and Hard Reset 2 32 2 6 4 Pull Up Pull Down 2 32 2 6 4 1 Pull Up Pull Down Enable and Disable for 5 V Only...

Page 5: ...Data Address Register DAR 3 23 3 9 4 Time Base Facility TB OEA 3 23 3 9 5 Decrementer Register DEC 3 23 3 9 6 Machine Status Save Restore Register 0 SRR0 3 23 3 9 7 Machine Status Save Restore Registe...

Page 6: ...Update Instructions 3 42 3 13 10 6 Floating Point Load Single Instructions 3 42 3 13 10 7 Floating Point Store Single Instructions 3 42 3 13 10 8 Optional Instructions 3 43 3 14 Virtual Environment Ar...

Page 7: ...ally Executed Instructions 3 60 3 15 6 Timer Facilities 3 61 3 15 7 Optional Facilities and Instructions 3 61 Chapter 4 Burst Buffer Controller 2 Module 4 1 Key Features 4 2 4 1 1 BIU Key Features 4 2...

Page 8: ...ADR 4 25 4 6 3 Decompressor Class Configuration Registers 4 25 Chapter 5 Unified System Interface Unit USIU Overview 5 1 Memory Map and Registers 5 2 5 1 1 USIU Special Purpose Registers 5 6 Chapter 6...

Page 9: ...2 3 SIU Interrupt Pending Register 3 SIPEND3 6 33 6 2 2 2 4 SIU Interrupt Mask Register SIMASK 6 33 6 2 2 2 5 SIU Interrupt Mask Register 2 SIMASK2 6 34 6 2 2 2 6 SIU Interrupt Mask Register 3 SIMASK3...

Page 10: ...et 7 3 7 1 7 Checkstop Reset 7 3 7 1 8 Debug Port Hard Reset 7 3 7 1 9 Debug Port Soft Reset 7 3 7 1 10 JTAG Reset 7 3 7 1 11 ILBC Illegal Bit Change 7 3 7 2 Reset Actions Summary 7 3 7 3 Data Coheren...

Page 11: ...Flow 8 19 8 8 Basic Power Structure 8 21 8 8 1 General Power Supply Definitions 8 21 8 8 2 Chip Power Structure 8 22 8 8 2 1 NVDDL 8 22 8 8 2 2 QVDDL 8 22 8 8 2 3 VDD 8 22 8 8 2 4 VDDSYN VSSSYN 8 22...

Page 12: ...ransfer 9 17 9 5 5 Burst Mechanism 9 18 9 5 6 Alignment and Packaging of Transfers 9 29 9 5 7 Arbitration Phase 9 32 9 5 7 1 Bus Request 9 33 9 5 7 2 Bus Grant 9 33 9 5 7 3 Bus Busy 9 34 9 5 7 4 Inter...

Page 13: ...tup Time 10 8 10 3 Chip Select Timing 10 10 10 3 1 Memory Devices Interface Example 10 12 10 3 2 Peripheral Devices Interface Example 10 13 10 3 3 Relaxed Timing Examples 10 14 10 3 4 Extended Hold Ti...

Page 14: ...8 11 6 2 L2U Reservation Support 11 8 11 6 3 Reserved Location Bus and Possible Actions 11 9 11 7 L Bus Show Cycle Support 11 9 11 7 1 Programming Show Cycles 11 10 11 7 2 Performance Impact 11 10 11...

Page 15: ...13 5 13 3 Programming the QADC64E Registers 13 7 13 3 1 QADC64E Module Configuration Register QADMCR 13 8 13 3 1 1 Low Power Stop Mode 13 9 13 3 1 2 Freeze Mode 13 9 13 3 1 3 Switching Between Legacy...

Page 16: ...er Continuous Scan Mode 13 46 13 5 4 4 3 External Gated Continuous Scan Mode 13 46 13 5 4 4 4 Periodic Interval Timer Continuous Scan Mode 13 47 13 5 5 QADC64E Clock QCLK Generation 13 47 13 5 6 Perio...

Page 17: ...Address Space 14 10 14 3 2 QADC64E Interrupt Register 14 11 14 3 3 Port Data Register 14 12 14 3 4 Port Data Direction Register 14 13 14 3 5 Control Register 0 14 14 14 3 6 Control Register 1 14 16 1...

Page 18: ...3 Interface 14 51 14 4 7 1 QADC64E Bus Interface Unit 14 51 14 4 7 2 QADC64E Bus Accessing 14 51 14 5 Trigger and Queue Interaction Examples 14 53 14 5 1 Queue Priority Schemes 14 53 14 5 2 Conversion...

Page 19: ...ol Register 2 SPCR2 15 20 15 6 1 4 QSPI Control Register 3 SPCR3 15 20 15 6 1 5 QSPI Status Register SPSR 15 21 15 6 2 QSPI RAM 15 22 15 6 2 1 Receive RAM 15 23 15 6 2 2 Transmit RAM 15 23 15 6 2 3 Co...

Page 20: ...ueue Operation of SCI1 for Transmit and Receive 15 59 15 8 2 Queued SCI1 Status and Control Registers 15 59 15 8 2 1 QSCI1 Control Register QSCI1CR 15 60 15 8 2 2 QSCI1 Status Register QSCI1SR 15 61 1...

Page 21: ...Receive Process 16 14 16 4 4 1 Receive Message Buffer Deactivation 16 16 16 4 4 2 Locking and Releasing Message Buffers 16 16 16 4 5 Remote Frames 16 17 16 4 6 Overload Frames 16 17 16 5 Special Opera...

Page 22: ...Interface Submodule MBISM 17 13 17 6 1 MIOS14 Bus Interface MBISM Registers 17 13 17 6 1 1 MIOS14 Test and Signal Control Register MIOS14TPCR 17 13 17 6 1 2 MIOS14 Vector Register MIOS14VECT 17 14 17...

Page 23: ...Operation 17 34 17 9 3 5 2 Single Output Compare Operation 17 35 17 9 3 5 3 Output Port Bit Operation 17 36 17 9 3 6 Output Pulse Width Modulation OPWM Mode 17 36 17 9 4 Modular I O Bus MIOB Interfac...

Page 24: ...7 11 8 MPIOSM Register Organization 17 62 17 11 8 1 MPIOSM Data Register MPIOSMDR 17 62 17 11 8 2 MPIOSM Data Direction Register MPIOSMDDR 17 63 17 12 MIOS14 Interrupts 17 63 17 12 1 MIOS14 Interrupt...

Page 25: ...18 9 18 3 2 4 T2CLK 18 10 18 3 3 PPM Module Pad Configuration 18 10 18 4 PPM Registers 18 10 18 4 1 Module Configuration Register PPMMCR 18 10 18 4 1 1 Entering Stop Mode 18 11 18 4 2 PPM Control Regi...

Page 26: ...DSCR 19 12 19 4 3 Development Support Status Register DSSR 19 13 19 4 4 TPU3 Interrupt Configuration Register TICR 19 14 19 4 5 Channel Interrupt Enable Register CIER 19 15 19 4 6 Channel Function Sel...

Page 27: ...isters 21 5 21 2 1 1 Register Addressing 21 5 21 2 1 2 UC3F EEPROM Configuration Register UC3FMCR 21 5 21 2 1 3 UC3F EEPROM Extended Configuration Register UC3FMCRE 21 8 21 2 1 4 UC3F EEPROM High Volt...

Page 28: ...ion 22 1 Features 22 1 22 2 CALRAM Block Diagram 22 2 22 3 CALRAM Memory Map 22 2 22 4 Modes of Operation 22 4 22 4 1 Reset 22 5 22 4 2 One Cycle Mode 22 5 22 4 2 1 CALRAM Access Privilege Violations...

Page 29: ...truction Fetch Show Cycle Control 23 7 23 2 Watchpoints and Breakpoints Support 23 7 23 2 1 Internal Watchpoints and Breakpoints 23 9 23 2 1 1 Restrictions 23 11 23 2 1 2 Byte and Half Word Working Mo...

Page 30: ...erial Data Into Development Port 23 35 23 4 6 10 Serial Data Out of Development Port 23 36 23 4 6 11 Fast Download Procedure 23 37 23 5 Software Monitor Debugger Support 23 38 23 5 1 Freeze Indication...

Page 31: ...ped Locations Via the Auxiliary Port 24 18 24 6 3 Accessing READI Tool Mapped Registers Via the Auxiliary Port 24 19 24 6 4 Partial Register Updates 24 19 24 6 5 Programming Considerations 24 20 24 6...

Page 32: ...essage 24 45 24 8 2 5 Error Messages 24 46 24 8 2 6 Relative Addressing 24 46 24 8 3 Queue Overflow Program Trace Error Message 24 47 24 8 4 Branch Trace Message Operation 24 47 24 8 4 1 BTM Capture a...

Page 33: ...24 10 5 Error Handling 24 65 24 10 5 1 Access Alignment 24 65 24 10 5 2 L Bus Address Error 24 65 24 10 5 3 L Bus Data Error 24 65 24 10 6 Exception Sequences 24 66 24 10 7 Secure Mode 24 66 24 10 8...

Page 34: ...CPU Development Access Flow Diagram 24 81 24 14 3 Throughput 24 82 24 14 4 Development Access Timing Diagrams 24 82 24 15 Power Management 24 86 24 15 1 Functional Description 24 86 24 15 2 Low Power...

Page 35: ...ss A 8 A 2 9 2 Single Segment Full Compression CLASS_1 A 9 A 2 9 3 Twin Segment Full Compression CLASS_2 A 9 A 2 9 4 Left Segment Compression and Right Segment Bypass CLASS_3 A 10 A 2 9 5 Left Segment...

Page 36: ...Time Accumulator PTA D 3 D 3 Queued Output Match TPU3 Function QOM D 5 D 4 Table Stepper Motor TSM D 7 D 5 Frequency Measurement FQM D 10 D 6 Universal Asynchronous Receiver Transmitter UART D 12 D 7...

Page 37: ...e F 2 F 2 EMI Characteristics F 2 F 2 1 Reference Documents F 2 F 2 2 Definitions and Acronyms F 3 F 2 3 EMI Testing Specifications F 3 F 3 Thermal Characteristics F 3 F 3 1 Thermal References F 5 F 4...

Page 38: ...3 Ball Map F 86 Appendix G 66 MHz Electrical Characteristics G 1 66 MHz Feature Limitations G 1 G 2 Package G 3 G 3 EMI Characteristics G 3 G 3 1 Reference Documents G 3 G 3 2 Definitions and Acronyms...

Page 39: ...teristics G 56 G 18 TPU3 Electrical Characteristics G 57 G 19 TouCAN Electrical Characteristics G 58 G 20 PPM Timing Characteristics G 58 G 21 MIOS Timing Characteristics G 59 G 21 1 MPWMSM Timing Cha...

Page 40: ...MPC561 MPC563 Reference Manual Rev 1 2 xl Freescale Semiconductor Contents Paragraph Number Title Page Number...

Page 41: ...CR 3 16 3 8 Integer Exception Register XER 3 18 3 9 Link Register LR 3 19 3 10 Count Register CTR 3 19 3 11 Machine State Register MSR 3 20 3 12 DAE Source Instruction Service Register DSISR 3 22 3 13...

Page 42: ...ing Register 2 SIPEND2 6 32 6 17 SIU Interrupt Pending Register 3 SIPEND3 6 33 6 18 SIU Interrupt Mask Register SIMASK 6 34 6 19 SIU Interrupt Mask Register 2 SIMASK2 6 34 6 20 SIU Interrupt Mask Regi...

Page 43: ...3 Clocks 8 8 8 5 General System Clocks Select 8 11 8 6 Divided System Clocks Timing Diagram 8 12 8 7 Clocks Timing For DFNH 1 or DFNL 0 8 13 8 8 Clock Source Switching Flow Chart 8 15 8 9 Low Power Mo...

Page 44: ...24 Bus Arbitration Flowchart 9 33 9 25 Master Signals Basic Connection 9 34 9 26 Bus Arbitration Timing Diagram 9 35 9 27 Internal Bus Arbitration State Machine 9 36 9 28 Termination Signals Protocol...

Page 45: ...aster Configuration for GPCM Handled Memory Devices 10 29 10 21 Synchronous External Master Basic Access GPCM Controlled 10 30 10 22 Memory Controller Status Register MSTAT 10 32 10 23 Memory Controll...

Page 46: ...d Signed Result Format LJSRR 13 33 13 19 Left Justified Unsigned Result Register LJURR 13 33 13 20 QADC64E Analog Subsystem Block Diagram 13 34 13 21 Conversion Timing 13 35 13 22 Bypass Mode Conversi...

Page 47: ...14 6 14 4 Module Configuration Register QADCMCR 14 8 14 5 QADC Interrupt Register QADCINT 14 12 14 6 Interrupt Levels on IRQ with ILBS 14 12 14 7 Port A Data Register PORTQA Port B Data Register PORTQ...

Page 48: ...46 Gated Mode Continuous Scan Timing 14 65 14 47 Equivalent Analog Input Circuitry 14 66 14 48 Errors Resulting from Clipping 14 67 14 49 Star Ground at the Point of Power Supply Origin 14 69 14 50 E...

Page 49: ...ter QSCI1CR 15 60 15 32 QSCI1 Status Register QSCI1SR 15 61 15 33 Queue Transmitter Block Enhancements 15 63 15 34 Queue Transmit Flow 15 66 15 35 Queue Transmit Software Flow 15 66 15 36 Queue Transm...

Page 50: ...tion Register MIOS14MCR 17 15 17 8 MCPSM Block Diagram 17 16 17 9 MCPSM Status Control Register MCPSMSCR 17 18 17 10 MMCSM Block Diagram 17 20 17 11 MMCSM Modulus Up Counter 17 20 17 12 MMCSM Up Count...

Page 51: ...ck Diagram of PPM Module 18 4 18 3 Internal Multiplexer Mechanism for Transmit Data 18 5 18 4 Internal Multiplexer Mechanism for Received Data 18 5 18 5 PPM Clocks and Serial Data Signals 18 6 18 6 On...

Page 52: ...1 19 17 19 16 HSRR0 Host Service Request Register 0 19 17 19 17 HSRR1 Host Service Request Register 1 19 17 19 18 CPR0 Channel Priority Register 0 19 18 19 19 CPR1 Channel Priority Register 1 19 18 1...

Page 53: ...13 23 3 Instruction Support General Structure 23 15 23 4 Load Store Support General Structure 23 18 23 5 Functional Diagram of MPC561 MPC563 Debug Mode Support 23 21 23 6 Debug Mode Logic 23 23 23 7...

Page 54: ...d 24 34 24 16 Enabling Program Trace Out of System Reset 24 36 24 17 READI Mode Selection 24 36 24 18 READI Module Disabled 24 37 24 19 Direct Branch Message Format 24 38 24 20 Indirect Branch Message...

Page 55: ...w Format 24 54 24 49 Data Trace Flow Diagram for Non Pipelined Access 24 55 24 50 Date Write Message 24 57 24 51 Data Read Message 24 58 24 52 Data Write Synchronization Message 24 58 24 53 Data Read...

Page 56: ...85 24 88 DSDI Data Message CPU Instruction rfi 24 85 24 89 DSDO Data Message CPU Data Out 24 86 25 1 Pin Requirement on JTAG 25 1 25 2 Test Logic Block Diagram 25 3 25 3 JTAG Mode Selection 25 3 25 4...

Page 57: ...Parameters Slave Edge Aligned Mode D 24 D 14 MCPWM Parameters Slave Ch A Non Inverted Center Aligned Mode D 26 D 15 MCPWM Parameters Slave Ch B Non Inverted Center Aligned Mode D 27 D 16 MCPWM Paramet...

Page 58: ...Read Timing GPCM Controlled TRLX 0 ACS 11 F 35 F 19 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 F 36 F 20 Address Show Cycle Bus Timing F 36 F 21 Address and Data Show Cycle Bus Timi...

Page 59: ...unter Bus Capture Timing Diagram F 70 F 59 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram F 70 F 60 MDASM Minimum Output Pulse Width Timing Diagram F 71 F 61 Counter Bus to MDASM Output Pin Ch...

Page 60: ...G 26 Interrupt Detection Timing for External Edge Sensitive Lines G 41 G 27 Debug Port Clock Input Timing G 42 G 28 Debug Port Timings G 42 G 29 Auxiliary Port Data Input Timing Diagram G 43 G 30 Auxi...

Page 61: ...Pin To Counter Bus Capture Timing Diagram G 66 G 58 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram G 66 G 59 MDASM Minimum Output Pulse Width Timing Diagram G 66 G 60 Counter Bus to MDASM Outp...

Page 62: ...MPC561 MPC563 Reference Manual Rev 1 2 lxii Freescale Semiconductor Figures Figure Number Title Page Number...

Page 63: ...MPC561 MPC563 Mode Selection Options 2 29 2 14 MPC561 MPC563 Signal Reset State 2 34 3 1 RCPU Execution Units 3 4 3 2 Supervisor Level SPRs 3 9 3 3 Development Support SPRs 3 11 3 4 FPSCR Bit Categori...

Page 64: ...n 3 57 3 36 Register Settings Following a Data Protection Error Exception 3 59 3 37 Register Settings Following a Debug Exception 3 60 3 38 Register Settings for Data Breakpoint Match 3 60 4 1 Excepti...

Page 65: ...on Taken for Each Reset Cause 7 4 7 2 Reset Configuration Word and Data Corruption Coherency 7 4 7 3 Reset Status Register Bit Descriptions 7 5 7 4 Reset Configuration Options 7 7 7 5 RCW Bit Descript...

Page 66: ...criptions 10 36 10 12 DMOR Bit Descriptions 10 38 11 1 DMPU Registers 11 6 11 2 Reservation Snoop Support 11 9 11 3 L2U_MCR LSHOW Modes 11 10 11 4 L2U Show Cycle Support Chart 11 12 11 5 L2U PPC Regis...

Page 67: ...r Events 13 54 13 23 Status Bits 13 55 13 24 External Circuit Settling Time to 1 2 LSB 10 Bit Conversions 13 75 13 25 Error Resulting from Input Leakage IOFF 13 76 14 1 QADC64E_A Address Map 14 3 14 2...

Page 68: ...CM Pin Functions 15 12 15 10 PQSPAR Bit Descriptions 15 13 15 11 DDRQS Bit Descriptions 15 14 15 12 QSPI Register Map 15 16 15 13 SPCR0 Bit Descriptions 15 18 15 14 Bits Per Transfer 15 18 15 15 SPCR1...

Page 69: ...6 28 16 16 CANCTRL1 Bit Descriptions 16 29 16 17 PRESDIV Bit Descriptions 16 30 16 18 CANCTRL2 Bit Descriptions 16 30 16 19 TIMER Bit Descriptions 16 31 16 20 RXGMSKHI RXGMSKLO Bit Descriptions 16 32...

Page 70: ...Descriptions 17 58 17 28 MPWMCNTR Bit Descriptions 17 58 17 29 MPWMSCR Bit Descriptions 17 59 17 30 PWMSM Output Signal Polarity Selection 17 59 17 31 Prescaler Values 17 60 17 32 MPIOSM I O Signal F...

Page 71: ...iption 19 15 19 11 CIER Bit Descriptions 19 15 19 12 CFSRn Bit Descriptions 19 16 19 13 HSQRn Bit Descriptions 19 17 19 14 HSSRn Bit Descriptions 19 18 19 15 CPRn Bit Description 19 18 19 16 Channel P...

Page 72: ...ore Watchpoints Programming Options 23 17 23 9 Check Stop State and Debug Mode 23 27 23 10 Trap Enable Data Shifted into Development Port Shift Register 23 34 23 11 Debug Port Command Shifted Into Dev...

Page 73: ...MSEO Protocol 24 23 24 19 Public Messages Supported 24 24 24 20 Error Message Codes 24 27 24 21 Vendor Defined Messages Supported 24 27 24 22 Message Field Sizes 24 29 24 23 Indirect Branch Message 24...

Page 74: ...14 Modular Input Output Subsystem B 18 B 14 TouCAN A B and C CAN 2 0B Controller B 26 B 15 UIMB U Bus to IMB Bus Interface B 31 B 16 CALRAM Control Registers B 31 B 17 CALRAM Array B 32 B 18 READI Mod...

Page 75: ...aracteristics F 69 F 27 MPIOSM Timing Characteristics F 71 F 28 MPC561 MPC563 Signal Names and Pin Names F 73 G 1 Absolute Maximum Ratings VSS 0V G 1 G 2 Thermal Characteristics G 3 G 3 ESD Protection...

Page 76: ...cale Semiconductor G 22 PPM Timing G 58 G 23 MCPSM Timing Characteristics G 60 G 24 MPWMSM Timing Characteristics G 60 G 25 MMCSM Timing Characteristics G 62 G 26 MDASM Timing Characteristics G 64 G 2...

Page 77: ...tions programmers who want to develop products for the MPC561 MPC563 It is assumed that the reader understands operating systems and microprocessor and microcontroller system design Organization Follo...

Page 78: ...gacy mode which is the default mode of operation Chapter 14 QADC64E Enhanced Mode Operation The two queued analog to digital converter QADC modules on the MPC561 MPC563 devices are 10 bit unipolar suc...

Page 79: ...MPC561 MPC563 Chapter 24 READI Module The READI module provides development support capabilities for MCUs in single chip mode without requiring address and data signals for internal visibility Chapter...

Page 80: ...for 32 Bit Implementations of the PowerPC Architecture MPCFPE32B AD Describes resources defined by the PowerPC architecture Reference manuals These books provide details about individual implementatio...

Page 81: ...ple DATA 24 31 form the least significant byte of the data bus x In some contexts such as signal encodings x indicates a don t care n Used to express an undefined numerical value NOT logical operator...

Page 82: ...Not equal AND Inclusive OR OR Exclusive OR EOR NOT Complementation Concatenation Transferred Exchanges Sign bit also used to show tolerance Sign extension Table ii Acronyms and Abbreviated Terms Term...

Page 83: ...re unit MSB Most significant bit MSR Machine state register NaN Not a number No op No operation OEA Operating environment architecture PLL Phase locked loop POR Power on reset PVR Processor version re...

Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...

Page 85: ...ller and enhanced interrupt controller EIC 512 Kbytes of Flash EEPROM memory available on the MPC563 only Typical endurance of 100 000 write erase cycles 25 C Typical data retention of 100 years 25 C...

Page 86: ...ball grid array PBGA packaging 388 ball PBGA 27 mm x 27 mm body size 1 0 mm ball pitch Default 40 and optional 56 and 66 MHz operation 40 C 125 C Independent power supplies 5 V I O 5 0 0 25 V 2 6 0 1...

Page 87: ...llowing sections 1 3 1 High Performance CPU System Fully static design Four major power saving modes On doze sleep deep sleep and power down E Bus L Bus U Bus IMB3 USIU Buffer Burst L2U UIMB QSMCM MIO...

Page 88: ...base Clock synthesizer Power management Reset controller External bus interface that tolerates 5 V inputs provides 2 6 V outputs and supports multi master designs Enhanced interrupt controller that su...

Page 89: ...gion size support Supports enhanced external burst Up to eight beat transfer bursts two clock minimum bus transactions Use with SRAM EPROM Flash and other peripherals Byte selects or write enables 32...

Page 90: ...3 of the IEEE ISTO 5001 1999 Program trace via branch trace messaging BTM Data trace via data write messaging DWM and data read messaging DRM Ownership trace via ownership trace messaging OTM Run tim...

Page 91: ...m conversion time of 7 s with typical QCLK frequency 2 MHz and 2 bits accuracy Two conversion command queues of variable length Automated queue modes initiated by External edge trigger Software comman...

Page 92: ...e 16 register receive buffers and 16 register transmit buffers on one SCI Advanced error detection and optional parity generation and detection Word length programmable as eight or nine bits Separate...

Page 93: ...ice offering in the MPC500 family to the MPC561 MPC563 Table 1 2 Differences Between MPC555 and MPC561 MPC563 Module MPC555 MPC561 MPC563 CPU Core Identical BBC Basic Enhanced Code Compression classes...

Page 94: ...3 QSMCM UIMB Core L2U No changes BBC2 Enhanced interrupt controller support Enhanced exception relocation table Branch target buffer 2 Kbytes of decompression RAM for code compression This may also be...

Page 95: ...t down The IRAMSTBY pin can be powered directly from a battery using an internal shunt regulator or via a small battery for standby use See Figure 1 2 Figure 1 2 Recommended Connection Diagram for IRA...

Page 96: ...g sections Refer to Figure 1 4 Flash memory 512 Kbytes CALRAM static RAM memory 32 Kbytes Control registers and IMB3 modules 64 Kbytes BBC control registers 16 Kbytes USIU and Flash control registers...

Page 97: ...es Reserved L bus Mem 464 Kbytes CALRAM 32 Kbytes 0x3F F000 0x30 0000 0x30 7FFF DPTRAM 8 Kbytes QSMCM 1 Kbyte MIOS14 4 Kbytes TouCAN_A 1 Kbyte TouCAN_B 1 Kbyte UIMB Registers 128 bytes TPU3_A 1 Kbyte...

Page 98: ...Map 1 9 Supporting Documentation List This list contains references to currently available and planned documentation MPC555 User s Manual MPC555UM AD RCPU Reference Manual RCPURM AD Nexus Standard Spe...

Page 99: ...ive low for example TA transfer acknowledge Active low signals are referred to as asserted active when they are low and negated when they are high Signals that are not active low such as ADDR 8 31 add...

Page 100: ...WR RD BURST BDIP TA TEA OE TEXP RSTCONF STS BI TS Interrupt Development XTAL EXTAL XFC PULL_SEL CLKOUT EXTCLK ENGCLK BUCLK VDDSYN VSSSYN Clocks and A_CNTX0 A_CNRX0 B_CNTX0 B_CNRX0 TouCAN EPEE B0EPEE V...

Page 101: ...te Indicates the direction of the data transfer for a transaction A logic one indicates a read from a slave device a logic zero indicates a write to a slave device BURST 1 I O BURST Burst Indicator Dr...

Page 102: ...s sampled from the external data bus When this line is negated the configuration mode adopted by the MPC561 MPC563 is either the internal default or read from the internal Flash MPC563 only O Timer Ex...

Page 103: ...nterrupt Request 2 One of the eight external signals that can request by means of the internal interrupt controller a service routine from the RCPU I Cancel Reservation Instructs the MPC561 MPC563 to...

Page 104: ...T TRST in order to configure the PLL clock mode of operation CS 0 3 4 O CS 0 3 Chip Select 0 3 These output signals enable peripheral or memory devices at programmed addresses if defined appropriately...

Page 105: ...apter 7 Reset for more details on timing SRESET 1 I O SRESET Soft Reset The reset controller can detect an external assertion of SRESET only if it occurs while the MPC561 MPC563 is not asserting reset...

Page 106: ...eport the number of instructions flushed from the instruction queue in the internal core See Chapter 23 Development Support for more details O Instruction Watchpoint 2 This output signal reports the d...

Page 107: ...ee Section 2 5 Test Clock This input provides a clock for on board test logic JTAG I Development Serial Clock This input signal is the clock for the debug port interface See Chapter 23 Development Sup...

Page 108: ...e drive voltage is configured using the EECLK 0 1 bits in the SCCR register in the SIU O BUCLK When the MPC561 MPC563 is in limp mode it is operating from a less precise on chip ring oscillator to all...

Page 109: ...VSSF Flash core ground reference Available in the MPC563 only This signal is not connected on the MPC561 QADC64E_A and QADC64E_B ETRIG 1 2 PCS 6 7 2 I ETRIG 1 2 ETRIG 1 2 These are the external trigge...

Page 110: ...4 7 This is a bidirectional general purpose I O if the QADC64E is configured in enhanced mode otherwise it is an input only A_AN 52 54 A_MA 0 2 A_PQA 0 2 3 I A_AN 52 54 Analog Input 52 54 Input only...

Page 111: ...a bidirectional general purpose I O if the QADC64E is configured in enhanced mode otherwise it is an input only B_AN 48 51 B_PQB 4 7 4 I B_AN 48 51 Analog Input 48 51 Analog input channel The input is...

Page 112: ...output from the QSPI in slave mode I O Port QGPIO4 When this signal is not needed for a QSPI application it can be configured as a general purpose input output MOSI QGPIO5 1 I O QGPIO5 Master Out Sla...

Page 113: ...the receive enable bit in the SCI control register is set to a logic 1 this signal cannot function as a general purpose input I TouCAN Receive Data This is the serial data input signal for the TouCAN_...

Page 114: ...uencies Clock Input MPWM16 can provide a clock input to modulus clock submodule MMCSM8 MPWM17 MDO3 1 I O MPWM17 unless the Nexus READI port is enabled See Section 2 5 Pulse Width Modulation 17 This si...

Page 115: ...flow tracking is required VF reports the number of instructions flushed from the instruction queue in the internal core VF signals are also multiplexed with the development and debug signals VF0 LWP1...

Page 116: ...t O READI Message Data Out Message data out MDO5 is an output signal used for uploading OTM BTM DTM and read write accesses External latching of MDO occurs on rising edge of MCKO Eight MDO signals are...

Page 117: ...This signal provides QSPI peripheral chip select when the enhanced PCS mode is selected B_TPUCH 0 15 16 I O B_TPUCH 0 15 Provides TPU module B with 16 input output programmable timed events B_T2CLK PC...

Page 118: ...3 MPC564 have Flash memory 5 The input only applies in legacy mode 6 C_CNTX0 and C_CNRX0 can be shared either with the MIOS14 GPIO pins MPIO32B12 MPIO32B11 or with the QSMCM SC12 pins TXD2 QGPO2 RXD2...

Page 119: ...TAG mode DSDI in BDM mode MDI0 TDI DSDI TDO DSDO MDO0 MDO0 TDO DSDO2 2 TDO in JTAG mode DSDO in BDM mode VF0 MPIO32B0 MDO1 MDO1 VF0 MPIO32B03 3 Selected by the VF bit in the MIOS14TPCR VF1 MPIO32B1 MC...

Page 120: ...or the slew rate refer to Appendix F Electrical Characteristics 0 Slew rate controlled 1 Not slew rate controlled SLRC1 controls the slew rate of signals on the following modules QSPI TouCAN_A TouCAN_...

Page 121: ...his signal Refer to Table 2 14 for more information on SPRDS 8 T2CLK_PU Controls the pull up on the TPU T2CLK signals 0 Pull ups are enabled if the T2CLK signals are defined as inputs 1 Pull ups are d...

Page 122: ...PM_TX1 MPWM3 PPM_RX1 MPIO32B10 PPM_TSYNC MPIO32B13 PPM_TCLK Refer to Table 2 8 14 15 Reserved 16 PPMV Selects the voltage of the PPM pads 0 The voltage will be 2 6 V 1 The voltage will be 5 V 17 19 Re...

Page 123: ...PIO32B11 C_CNRX0 MPIO32B12 C_CNTX0 00 TXD2 QGPO2 RXD2 QGPI2 MPIO32B11 MPIO32B12 x1 TXD2 QGPO2 RXD2 QGPI2 C_CNRX0 C_CNTX0 10 C_CNTX0 C_CNRX0 MPIO32B11 MPIO32B12 Table 2 8 PPMPAD Pad Functionalities PPM...

Page 124: ...CLK Also shown in this table is the internal connection of the TPU signals when the enhanced chip select function is used 0010 00000100 11111011 0011 00001000 11110111 0100 00010000 11101111 0101 0010...

Page 125: ...1 1 1 PCS5 PCS4 A_T2CLK Signal driven HI internally B_T2CLK Signal driven HI internally by connection to A_T2CLK 1 If PCS4 5EN 1 then A B_T2CLK into the module is pulled up internally enabling Div 8 c...

Page 126: ...ETRIG2 0 0 1 1 1 ETRIG1 ETRIG2 Disabled A_TPUCH15 B_TPUCH15 0 1 0 0 0 ETRIG1 PCS7 Enabled ETRIG1 PCS7 0 1 0 1 1 ETRIG1 PCS7 Enabled A_TPUCH15 B_TPUCH15 0 1 1 0 0 ETRIG1 PCS7 Disabled ETRIG1 PCS7 0 1 1...

Page 127: ...events Assert PORESET TRST to reset the JTAG TAP controller Hold JCOMP RSTI high prior to PORESET TRST negation and keep high as long as JTAG mode is required The READI module will be held inactive s...

Page 128: ...ailable full port mode and reduced port mode Reduced port mode allows for a 1 bit input stream and a 2 bit output stream Full port mode allows for a 2 bit input stream and an 8 bit output stream If MD...

Page 129: ...he post reset functionality of some multiplexed signals For details on these signals and how they are configured refer to Section 7 5 2 Hard Reset Configuration Word The 2 6 V bus related signals have...

Page 130: ...onality the pull up or pull down devices are either disabled immediately at the negation of reset or remain enabled as shown in Table 2 14 Because hard reset can occur when a bus cycle is pending the...

Page 131: ...on the MIOS14 and TPU signals A low enables pull down devices Note that the pull devices can be disabled by the PULL_DIS0 MIOS14 and PRDS TPU bits in the PDMCR register See Section 2 3 Pad Module Con...

Page 132: ...5 V Yes 50 50 5 PD until PRDS is set No IRQ0 2 6 V No NA PU2 6 until PRDS is set8 Yes MDO4 if the Nexus READI port is enabled IRQ0 otherwise See Section 2 5 SGPIOC07 2 6 V No 50 25 Yes MDO4 7 2 6 V No...

Page 133: ...MODCK 2 3 11 2 6 V No NA PU2 6 until reset negates No PULL_SEL 5 V No NA PU5 external pull device required No PULL_SEL TSIZ 0 1 7 2 6 V No 50 25 PD when driver not enabled or until SPRDS is set No TS...

Page 134: ...7 2 6 V No 50 25 PU2 6 until reset negates No CS 0 3 WE 0 3 7 2 6 V No 50 25 PU2 6 when driver not enabled or until SPRDS is set No Controlled by bit ATWC bit 12 of the reset configuration word See Ta...

Page 135: ...until SPRDS is set No Controlled by DBGC in reset config word See Table 6 8 VF2 7 2 6 V No 50 25 No IWP3 7 2 6 V No 50 25 No IWP 0 1 7 2 6 V No 50 25 PU2 6 until reset negates No Controlled by DBGC i...

Page 136: ...V 5 V NA NA NA NA No ENGCLK 2 6 V BUCLK 2 6 V NA NA NA NA No QSMCM PCS0 5 V Yes 50 50 PU5 until PULL_DIS1 is set No QGPO0 SS 5 V Yes 50 50 No QGPIO0 5 V Yes 50 50 No PCS 1 3 5 V Yes 50 50 PU5 until P...

Page 137: ...5 MDI1 2 6 V No NA Yes MPWM1 3 5 V Yes 50 50 Pull device enabled until PULL_DIS0 is set 16 Yes MPWM1 unless the Nexus READI port is enabled then MDO2 See Section 2 5 MDO2 2 6 V No 50 25 No MPWM23 5 V...

Page 138: ...I port is enabled then MSEO See Section 2 5 VFLS0 2 6 V No 50 25 No MSEO 2 6 V No 50 25 No MPIO32B43 5 V Yes 50 50 5 Pull device enabled until PULL_DIS0 is set16 Yes MPIO32B4 VFLS1 2 6 V No 50 25 No M...

Page 139: ...ll device enabled until PRDS is set 16 Yes A_TPUCH 0 15 A_T2CLK 5 V Yes 50 50 PU5 when driver not enabled or until T2CLK_PU is set Yes A_T2CLK PCS5 5 V Yes 50 50 No B_TPUCH 0 15 5 V Yes 50 50 5 Pull d...

Page 140: ...PU5 when driver not enabled or until PULL_DIS2 is set No A_AN 52 54 A_MA 0 2 5 V Yes NA Yes A_PQA 0 2 5 V Yes 50 50 5 Yes A_AN 55 59 5 V Yes NA PU5 when driver not enabled or until PULL_DIS2 is set N...

Page 141: ...NA PU5 when driver not enabled or until PULL_DIS2 is set No B_AN 55 59 B_PQA 3 7 5 V Yes 50 50 5 Yes TouCAN_A TouCAN_B A_CNTX0 5 V Yes 50 50 17 PU5 until PULL_DIS3 is set No A_CNTX0 B_CNTX0 5 V Yes 5...

Page 142: ...bled 4 Pull up pull down is active when pin is defined as an input and or during reset therefore output enable is negated This also means that external pull up pull down is NOT required unless specifi...

Page 143: ...K27S of the MPC561 15 These values represent full drive half drive and quarter drive 16 Whether the Pull device is a pull up or a pull down is determined by the state of the PULL_SEL signal 17 For thi...

Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...

Page 145: ...SC s use of simple instructions with rapid execution times yields high efficiency and throughput for PowerPC ISA based systems Most integer instructions execute in one clock cycle Instructions can com...

Page 146: ...PU FPR History FPR 32 X 64 Load Store Floating Data Load Integer Store Data Load Address Store ALU BFU IMUL IDIV GPR History GPR 32 X 32 Control Regs Next Address Generation Branch Unit Processor Inst...

Page 147: ...feed forwarding that control data dependencies in hardware Class code compression model support Efficient use of internal Flash MPC564 and external Flash MPC562 MPC564 by increasing code density up t...

Page 148: ...ranches can often be resolved early eliminating stalls caused by taken branches Table 3 1 summarizes the RCPU execution units Table 3 1 RCPU Execution Units Unit Description Branch processing unit BPU...

Page 149: ...oint registers execution of branch instructions is independent from execution of integer instructions The CR bits indicate conditions that may result from the execution of relevant instructions 3 4 2...

Page 150: ...either a source two register operand or to a 16 bit immediate value embedded in the instruction 3 4 4 Floating Point Unit FPU The FPU contains a double precision multiply array the floating point stat...

Page 151: ...rvisor mode typically used by the operating environment and user mode used by the application software The programming model incorporates 32 GPRs special purpose registers SPRs and several miscellaneo...

Page 152: ...t SPRs Condition Register Floating Point Status and Control Register FPSCR CR 0 31 0 31 0 31 GPR0 GPR1 GPR31 User Level SPRs Integer Exception Register XER Link Register LR Count Register CTR 0 31 0 6...

Page 153: ...6 Machine Status Save Restore Register 0 SRR0 for bit descriptions 27 Save and Restore Register 1 SRR1 See Section 3 9 7 Machine Status Save Restore Register 1 SRR1 for bit descriptions 80 External In...

Page 154: ...iptions 816 IMPU Region Attribute Register 0 MI_RA0 1 See Table 4 6 for bits descriptions 817 IMPU Region Attribute Register 1 MI_RA1 1 See Table 4 6 for bits descriptions 818 IMPU Region Attribute Re...

Page 155: ...iptions 147 Comparator D Value Register CMPD See Table 23 17 for bit descriptions 148 Exception Cause Register ECR See Table 23 18 for bit descriptions 149 Debug Enable Register DER See Table 23 19 fo...

Page 156: ...isters through operands in the instruction syntax 3 7 2 Floating Point Registers FPRs The PowerPC ISA architecture provides 32 64 bit FPRs These registers are accessed as source and destination regist...

Page 157: ...gister FPSCR The FPSCR controls the handling of floating point exceptions and records status resulting from the floating point operations FPSCR 0 23 are status bits FPSCR 24 31 are control bits FPSCR...

Page 158: ...he logical OR of all the floating point exception bits masked with their respective enable bits The mcrfs instruction implicitly clears FPSCR FEX if the result of the logical OR described above become...

Page 159: ...the value is less than greater than or equal to zero 16 Floating point less than or negative FL or 17 Floating point greater than or positive FG or 18 Floating point equal or zero FE or 19 Floating p...

Page 160: ...n instruction mcrxr to move to the CR from the XER Condition register logical instructions can be used to perform logical operations on specified bits in the condition register CR0 can be the implicit...

Page 161: ...point exception status For more information about the FPSCR see Section 3 7 3 Floating Point Status and Control Register FPSCR The bit settings for the CR1 field are shown in Table 3 8 3 7 4 3 Conditi...

Page 162: ...r rB algebraic comparison or rA SIMM UIMM or rB logical comparison For floating point compare instructions frA frB 2 Equal floating point equal EQ FE For integer compare instructions rA SIMM UIMM or r...

Page 163: ...s the branch target address for the branch conditional to count register bcctrx instructio 2 CA Carry CA In general the carry bit is set to indicate that a carry out of bit 0 occurred during execution...

Page 164: ...the mtmsr sc and rfi instructions It can be read by the mfmsr instruction 11 Table 3 11 shows the bit definitions for the MSR MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field POW 0 ILE SRESET 0000_0000...

Page 165: ...ating point loads stores and moves Floating point enabled program exceptions can still occur and the FPRs can still be accessed 1 The processor can execute floating point instructions and can take flo...

Page 166: ...SR DCMPEN should not be changed by software by a direct MSR register write MTMSR instruction It can be changed only by the RFI instruction or by an exception 30 RI Recoverable exception for machine ch...

Page 167: ...on such that all prior instructions have completed execution and no subsequent instruction has begun execution The instruction addressed by SRR0 may not have completed execution depending on the excep...

Page 168: ...e Status Save Restore Register 1 SRR1 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 SPRG0 SPRG1 SPRG2 SPRG3 Reset Unchanged Figure 3 16 SPRG0 SPRG3 Gene...

Page 169: ...R EE bits External Interrupt Enable EIE External Interrupt Disable EID and Non recoverable Interrupt NRI Issuing the mtspr instruction with one of these registers as an operand causes the RI and EE bi...

Page 170: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field SIE SRESET 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field DNC DNB DNA TR SRESET 0000_0000_0000_0000 Addr SPR 1022 Figure 3 1...

Page 171: ...ger logical instructions Integer rotate and shift instructions Floating point instructions which include floating point computational instructions as well as instructions that affect the floating poin...

Page 172: ...uctions PowerPC ISA compliant processors follow the program flow when they are in the normal execution state However the flow of instructions can be interrupted directly by the execution of an instruc...

Page 173: ...bD crbA crbB Condition Register OR with Complement crxor crbD crbA crbB Condition Register XOR divw divw divwo divwo rD rA rB Divide Word divwu divwu divwuo divwuo rD rA rB Divide Word Unsigned eieio...

Page 174: ...tiply Subtract Single frsp frsp frD frB Floating Round to Single fsub fsub frD frA frB Floating Subtract Double Precision fsubs fsubs frD frA frB Floating Subtract Single isync Instruction Synchronize...

Page 175: ...date Indexed lwzx rD rA rB Load Word and Zero Indexed mcrf crfD crfS Move Condition Register Field mcrfs crfD crfS Move to Condition Register from FPSCR mcrxr crfD Move to Condition Register from XER...

Page 176: ...B Shift Right Algebraic Word srawi srawi rA rS SH Shift Right Algebraic Word Immediate srw srw rA rS rB Shift Right Word stb rS d rA Store Byte stbu rS d rA Store Byte with Update stbux rS rA rB Store...

Page 177: ...le Word stswi rS rA NB Store String Word Immediate stswx rS rA rB Store String Word Indexed stw rS d rA Store Word stwbrx rS rA rB Store Word Byte Reverse Indexed stwcx rS rA rB Store Word Conditional...

Page 178: ...hanism allows the processor to change to supervisor state as a result of external signals errors or unusual conditions that arise in the execution of instructions When exceptions occur information abo...

Page 179: ...ons are ordered Ordered exceptions satisfy the following criteria Only one exception is reported at a time If for example a single instruction encounters multiple exception conditions those conditions...

Page 180: ...ruction Which instruction is addressed can be determined from the exception type and the status bits 4 Depending on the type of exception the instruction causing the exception may not have begun execu...

Page 181: ...re Emulation Section 3 15 4 13 Implementation Dependent Software Emulation Exception 0x1000 01100 Reserved 01200 Reserved 01300 Implementation Dependent Instruction Protection Exception Section 3 15 4...

Page 182: ...pleted 4 In the retirement stage the history buffer retires instructions in architectural order An instruction retires from the machine if it completes execution with no exceptions and if all instruct...

Page 183: ...nless otherwise noted reserved fields should be written with a zero when written and return a zero when read Thus this type of invalid form instructions yield results of the defined instructions with...

Page 184: ...fer the instruction pre fetch queue prior to execution If a program modifies the instructions it intends to execute it should call a system library program to ensure that the modifications have been m...

Page 185: ...orm any of the divisions in the divw o instruction 0x80000000 1 anything 0 then the contents of rD are 0x80000000 if Rc 1 the contents of bits in CR field 0 are LT 1 GT 0 EQ 0 and SO is set to the cor...

Page 186: ...h rA is in the range of registers to be loaded When rA is in range it is updated from memory 3 13 10 4 Storage Synchronization Instructions For these type of instructions EA must be a multiple of four...

Page 187: ...63 by using the CR and KR input signals Internal buses are snooped for RCPU accesses and the reservation mechanism can be used for multitask single master applications 3 14 2 Effect of Operand Placeme...

Page 188: ...n be accessed by an external system master 3 15 1 Branch Processor Registers 3 15 1 1 Machine State Register MSR The floating point exception mode encoding in the RCPU is as shown in Table 3 21 The SF...

Page 189: ...le interrupt NMI occurs when the IRQ0 is asserted and the following registers are set Table 3 22 Settings Caused by Reset Register Setting MSR IP depends on internal data bus configuration word ME is...

Page 190: ...chine check exception is assumed to be caused by one of the following conditions The accessed address does not exist A data error was detected A storage protection violation was detected by chip selec...

Page 191: ...apter 7 Reset for more details The register settings for machine check exceptions are shown in Table 3 25 Table 3 24 Machine Check Exception Processor Actions MSR ME Debug Mode Enable CHSTPE MCIE Acti...

Page 192: ...No change ME No change LE Bit is copied from ILE DCMPEN This bit is set according to BBCMCR EN_COMP AND BBCMCR EXC_COMP Other Cleared to 0 Data Storage Interrupt Status Register DSISR 3 0 14 Cleared t...

Page 193: ...0 from the physical base address indicated by MSR IP 3 15 4 6 Alignment Exception 0x00600 The following conditions cause an alignment exception The operand of a floating point load or store instructio...

Page 194: ...ge Interrupt Status Register DSISR 0 11 Cleared to 0 12 13 Cleared to 0 14 Cleared to 0 15 16 For instructions that use register indirect with index addressing set to bits 29 30 of the instruction For...

Page 195: ...ed exception is generated when the following condition is met as a result of a move to FPSCR instruction move to MSR mtmsr instruction or return from interrupt rfi instruction MSR FE0 MSR FE1 and FPSC...

Page 196: ...Register 1 SRR1 2 2 Only one of bits 11 13 and 14 can be set 0 10 Cleared to 0 11 Set for a floating point enabled program exception otherwise cleared 12 Cleared to 0 13 Set for a privileged instruct...

Page 197: ...er is altered by software and if bit 0 is changed from zero to one an interrupt request is signaled The register settings for the decrementer exception are shown in Table 3 30 Machine State Register M...

Page 198: ...stem call exception is taken instruction execution resumes at offset 0x00C00 from the physical base address indicated by MSR IP 3 15 4 11 Trace Exception 0x0D00 A trace interrupt occurs if MSR SE 1 an...

Page 199: ...g point assist exception A floating point assist exception also occurs when a tiny result is detected and the floating point underflow exception is disabled FPSCR UE 0 The register settings for floati...

Page 200: ...et when a software emulation exception occurs Save Restore Register 1 SRR1 1 4 Cleared to 0 10 15 Cleared to 0 Other Loaded from bits 16 31 of MSR In the current implementation bit 30 of the SRR1 is n...

Page 201: ...ression On mode the SRR0 register will contain a compressed address Table 3 35 Register Settings following an Instruction Protection Exception Register Name Bits Description Save Restore Register 0 SR...

Page 202: ...mentation Specific Data Protection Error Exception 0x1400 The implementation specific data protection error exception occurs in the following case The data access violates the storage protection and M...

Page 203: ...on Error Exception Register Name Bits Description Save Restore Register 0 SRR0 1 1 If the exception occurs during a data access in Decompression On mode the SRR0 register will contain the address of t...

Page 204: ...format All For I breakpoints set to the effective address of the instruction that caused the interrupt For L breakpoint set to the effective address of the instruction following the instruction that...

Page 205: ...ses except the first one causes the data storage protection error The implementation specific data storage protection interrupt is taken in this case For the update forms the update register rA is not...

Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...

Page 207: ...to relocate the RCPU exception vectors The IMPU always maps the exception vectors into the internal memory space of the MPC561 MPC563 This feature is important for a multi MPC561 MPC563 system where a...

Page 208: ...upports the decoupled interface with the RCPU instruction unit IMPU Registers U bus Slave Machine Address Buffer To Addresses IMPU DECRAM 2 Kbytes Decompressor Control Logic ICDU BTB RCPU Core Sequenc...

Page 209: ...led in software Global region entry declares the default access attributes for all memory areas not covered by the four regions The RCPU gets the instruction storage protection exception generated upo...

Page 210: ...target of historical change of flow COF address Four RAM entries 38 bits each which hold up to four valid instruction OPCODES 32 bits The six extra bits are used by ICDU in decompression on mode A 32...

Page 211: ...in the MPC561 MPC563 is useful if a user system implements burstable memory devices on the external bus Otherwise the mode will cause performance degradation when running code from external memory Whe...

Page 212: ...ncoding of the status bits is as follows SRR1 1 0 SRR1 3 Guarded storage SRR1 4 Protected storage or compression violation SRR1 10 0 Only one bit is set at a time 4 2 4 Slave Operation The BBC is oper...

Page 213: ...te the exception addresses of the RCPU The relocation feature always maps the exception addresses into the internal memory space of the MPC561 MPC563 See Figure 4 2 This feature is important in multi...

Page 214: ...ocation a branch instruction with absolute addressing ba must be placed Each ba instruction branches to the required exception routine These branch instructions should be successive in that region of...

Page 215: ...odule Configuration Register BBCMCR for programming details The ETR feature can be activated from reset by setting corresponding bits in the reset configuration word Table 4 1 Exception Addresses Mapp...

Page 216: ...ction 4 6 2 5 External Interrupt Relocation Table Implementation Dependent Instruction Storage Protection Error 0xFFF0 1300 Page_Offset 0x098 Implementation Dependent Data Storage Protection Error 0xF...

Page 217: ...it may be utilized for another purpose such as instruction code space or data space In order to activate the external interrupt relocation feature the following steps are required 1 Program the EIBAD...

Page 218: ...p memory address space It is a single port memory and may not be accessed simultaneously from the ICDU and U bus Interrupt Vector External Interrupt Handlers Table Interrupt Pointer by Core Internal M...

Page 219: ...n fetches or four clock access for read write data operations The base address of the DECRAM is 0x2F 8000 See Figure 4 6 The proper access rights to the DECRAM array may be defined by programming the...

Page 220: ...s running from the DECRAM should not also perform store operations to the DECRAM 4 4 1 1 Memory Protection Violations The DECRAM module does not acknowledge U bus accesses that violate the configurati...

Page 221: ...n FIFO replacement method Thus the BTB can support up to eight different branch target addresses in a program loop BTE Hit When the target address of a branch matches one of the valid BTE entries two...

Page 222: ...ited regarding some memory regions The BTB caching is inhibited for a region if the BTBINH bit is set in the region attribute register or global region attribute register See Instruction Buffers Instr...

Page 223: ...3 Decompressor class configuration registers DCCR block It consists of 15 decompression class configuration registers These registers are available for word wide read write accesses through U bus The...

Page 224: ...R block occupies addresses from 0x2F A000 to 0x2F A03F The address for non implemented memory blocks is not acknowledged and causes an error condition 784 0x2180 IMPU Region Base Address Register 0 MI...

Page 225: ...check exception for RCPU 0 DECRAM array is Readable and Writable 1 DECRAM array is Read only 1 D Data Only The DECRAM array may be used for Instructions and Data or for Data storage only Any attempt t...

Page 226: ...MP2 Exception Compression This bit determines the operation of the MPC562 MPC564 with exceptions If this bit is set the MPC562 MPC564 assumes that the all exception routine codes are compressed otherw...

Page 227: ...only DCAE bit should be set before vocabulary tables are loaded via the U bus 31 TST Reserved for BBC Test Operations 1 BE and BTEE should not both be set at the same time setting the BE bit disables...

Page 228: ...d PP attributes perform similar protection activities on a region The more protective attribute will be implied on the region if the attributes programming oppose each other Protection bits 00 Supervi...

Page 229: ...8 Kbytes 0000_0000_0000_0011_1111 256 Kbytes 0000_0000_0000_0111_1111 512 Kbytes 0000_0000_0000_1111_1111 1 Mbyte 0000_0000_0001_1111_1111 2 Mbytes 0000_0000_0011_1111_1111 4 Mbytes 0000_0000_0111_111...

Page 230: ...cess User No Access 01 Supervisor Fetch User No Access 1x Supervisor Fetch User Fetch 22 24 Reserved 25 G Guard attribute for region 0 Fetch is not prohibited from region Region is not guarded 1 Fetch...

Page 231: ...CR0 15 for the registers of the ICDU MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field BA HRESET Unchanged 000_0000_0000 Figure 4 11 External Interrup...

Page 232: ...Burst Buffer Controller 2 Module MPC561 MPC563 Reference Manual Rev 1 2 4 26 Freescale Semiconductor...

Page 233: ...32 levels for internal peripheral modules on the IMB bus It has an enhanced mode of operation which simplifies the MPC561 MPC563 interrupt structure and speeds up interrupt processing Additionally the...

Page 234: ...ating in peripheral mode or if accessed from an external master operating in debug mode BDM or Nexus Figure 5 1 shows the USIU block diagram Figure 5 1 USIU Block Diagram 5 1 Memory Map and Registers...

Page 235: ...s 0x2F C028 USIU General Purpose I O Data Register 2 SGPIODT2 See Table 6 24 for bit descriptions 0x2F C02C USIU General Purpose I O Control Register SGPIOCR See Table 6 25 for bit descriptions 0x2F C...

Page 236: ...ns 0x2F C11C Option Register 3 OR3 See Table 10 10 for bit descriptions 0x2F C120 0x2F C13C Reserved 0x2F C140 Dual Mapping Base Register DMBR See Table 10 11 for bit descriptions 0x2F C144 Dual Mappi...

Page 237: ...27C Reserved Clocks and Reset 0x2F C280 System Clock Control Register SCCR See Table 8 9 for bit descriptions 0x2F C284 PLL Low Power and Reset Control Register PLPRCR See Table 8 11 for bit descripti...

Page 238: ...rol Key RTCSCK See Table 8 8 for bit descriptions 0x2F C324 Real Time Clock Key RTCK See Table 8 8 for bit descriptions 0x2F C328 Real Time Alarm Seconds Key RTSECK See Table 8 8 for bit descriptions...

Page 239: ...pr 0 4 1 1 Bits 0 17 and 28 31 are all 0 0x2C00 Decrementer DEC See Section 3 9 5 Decrementer Register DEC for more information 22 0x1880 Time Base Lower Read TBL See Section 6 2 2 4 2 Time Base SPRs...

Page 240: ...Unified System Interface Unit USIU Overview MPC561 MPC563 Reference Manual Rev 1 2 5 8 Freescale Semiconductor...

Page 241: ...t request line to the RCPU Bus Monitor Section 6 1 5 Hardware Bus Monitor The SIU provides a bus monitor to watch internal to external accesses It monitors the transfer acknowledge TA response time fo...

Page 242: ...otection control register SYPCR if the software fails to service the SWT for a designated period of time e g because the software is trapped in a loop or lost After a system reset this function is ena...

Page 243: ...plexing and internal memory map location System configuration also includes a register containing part and mask number constants to identify the part in software System configuration registers include...

Page 244: ...ess the internal modules for debugging and backup purposes They provide access to the internal buses U bus and L bus and to the intermodule bus IMB3 There are two external master modes Peripheral mode...

Page 245: ...ction 6 2 2 1 2 Internal Memory Map Register IMMR for details The external master access is terminated by the TA TEA or RETRY signal on the external bus A deadlock situation might occur if an internal...

Page 246: ...ip select and attribute accordingly When trying to fetch an MPC561 MPC563 special register from an external master the address might be aliased to one of the external devices on the external bus If th...

Page 247: ...de Available When SC 10 Single Chip Mode with Trace Available When SC 11 Single Chip Mode SGPIOD 0 7 GDDR0 X X SGPIOD 8 15 GDDR1 X X SGPIOD 16 23 GDDR2 X X X SGPIOD 24 31 X SDDRD 23 31 X X X SGPIOC 0...

Page 248: ...interrupt vector into up to 48 vectors one for each source Automatic lower priority requests masking Full backward compatibility with MPC555 MPC556 enhanced mode is software programmable 6 1 4 2 Inte...

Page 249: ...d interrupt request and the decrementer exception when the decrementer MSB changes from 0 to 1 Level 2 Level 7 Level 6 Level5 Level 4 Level 3 Level 1 Level 0 IRQ 0 7 IREQ to RCPU NMI GEN USIU SWT I0 R...

Page 250: ...nfigured to more than one interrupt source the software should read the UIPEND register in the UIMB module and the particular status bits in order to identify which interrupt was asserted The interrup...

Page 251: ...ers The priority logic is provided in order to determine the highest unmasked interrupt request and interrupt code is generated in the SIVEC register See Table 6 4 NOTE If the enhanced interrupt contr...

Page 252: ...1100 8 IMB_IRQ 4 0x0040 00100000 9 IMB_IRQ 5 0x0048 00100100 10 IMB_IRQ 6 0x0050 00101000 11 IMB_IRQ 7 0x0058 00101100 12 EXT_IRQ2 0x0060 00110000 13 Level 2 0x0068 00110100 14 IMB_IRQ 8 0x0070 001110...

Page 253: ...34 IMB_IRQ 22 0x0110 10001000 35 IMB_IRQ 23 0x0118 10001100 36 EXT_IRQ6 0x0120 10010000 37 Level 6 0x0128 10010100 38 IMB_IRQ 24 0x0130 10011000 39 IMB_IRQ 25 0x0138 10011100 40 IMB_IRQ 26 0x0140 1010...

Page 254: ...4 The lower priority request masking feature is disabled by HRESET and it may be enabled by setting the LPMASK_EN bit in the SIUMCR register NOTE In the regular mode of the interrupt controller the l...

Page 255: ...ncoder 8 Interrupt Vector 6 from 48 Enables branch to the highest priority interrupt routine SIPEND2 SIPEND3 SIMASK2 SIMASK3 Interrupt Request to RCPU and IRQOUT pad U bus INT offset to branch table t...

Page 256: ...sing SIVEC MPC561 MPC563 Architecture Using SIVEC MPC561 MPC563 Architecture Using Enhanced Interrupt Controller Features Operation Details Interrupt propagation from request module to RCPU 8 clocks S...

Page 257: ...us accesses on the external bus The monitor counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge within bursts If the monitor times out transfer err...

Page 258: ...The state of the DEC is not affected by any resets and should be initialized by software The DEC runs continuously after power up once the time base is enabled by setting the TBE bit of the TBSCR see...

Page 259: ...uctions are used to move the lower half of the time base TBL while the mttbu and mftbu instructions are used to move the upper half TBU Two reference registers are associated with the time base TBREF0...

Page 260: ...egister After the timer reaches zero the PS bit is set and an interrupt is generated if the PIE bit is a logic one The software service routine should read the PS bit and then write a zero to terminat...

Page 261: ...quires a special service sequence to be executed on a periodic basis If this periodic servicing action does not occur the SWT times out and issues a reset or a non maskable interrupt NMI depending on...

Page 262: ...o a 16 bit decrementer clocked by the system clock An additional divide by 2048 prescaler is used if necessary The decrementer begins counting when loaded with a value from the software watchdog timin...

Page 263: ...ep or deep sleep the software watchdog timer is frozen It remains frozen and maintains its count value until the processor exits this state and resumes executing instructions The periodic interrupt ti...

Page 264: ...g with address 0x0000 0000 Refer to Figure 6 11 Figure 6 11 MPC561 MPC563 Memory Map 6 2 2 System Configuration and Protection Registers This section describes the MPC561 MPC563 registers 6 2 2 1 Syst...

Page 265: ...ster SIUMCR Table 6 7 SIUMCR Bit Descriptions Bits Name Description 0 EARB External arbitration 0 Internal arbitration is performed 1 External arbitration is assumed 1 3 EARP External arbitration requ...

Page 266: ...1 IRQ2 CR SGPIOC2 MTS functions as MTS 25 NOSHOW Instruction show cycles disabled If the NOSHOW bit is set 1 then all instruction show cycles are NOT transmitted to the external bus 26 EICEN Enhanced...

Page 267: ...Pins Configuration GPC Pin Function FRZ PTR SGPIOC6 IRQOUT LWP0 SGPIOC7 00 PTR LWP0 01 SGPIOC6 SGPIOC7 10 FRZ LWP0 11 FRZ IRQOUT Table 6 10 Single Chip Select Field Pin Configuration SC Pin Function...

Page 268: ...Q0 SGPIOC0 MDO4 IRQ1 RSV SGPIOC1 IRQ2 CR SGPIOC2 MTS IRQ3 KR RETRY SGPIOC3 IRQ4 AT2 SGPIOC4 IRQ5 SGPIOC5 MODCK11 1 Operates as MODCK1 during reset 00 IRQ0 IRQ1 IRQ22 2 This is true if MTSC is reset to...

Page 269: ...8 15 MASKNUM This read only field is mask programmed with a code corresponding to the mask number of the part It is intended to help factory test and user code which is sensitive to part changes 16 19...

Page 270: ...n word bit 16 The bit can also be written by software 0 Normal operation 1 Peripheral mode operation 17 SLVM Slave mode valid only if PRPM 0 In this mode an alternative master on the external bus can...

Page 271: ...a level interrupt the corresponding bit behaves in a manner similar to the bits associated with internal interrupt sources i e it reflects the status of the IRQ pin This bit can not be changed by sof...

Page 272: ...18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field SRESET 0000_0000_0000_0000 Figure 6 15 SIU Interrupt Pending Register SIPEND MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field IRQ0 LVL0 IMB IRQ0 IMB...

Page 273: ...to the RCPU SIMASK SIMASK2 SIMASK3 are updated by software and cleared upon reset It is the responsibility of the software to determine which of the interrupt sources are enabled at a given time NOTE...

Page 274: ...egister IRQ0 is a non maskable interrupt Figure 6 18 SIU Interrupt Mask Register SIMASK MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field IRQ01 LVL0 IMB IRQ0 IMB IRQ1 IMB IRQ2 IMB IRQ3 IRQ1 LVL1 IMB IRQ...

Page 275: ...can be read as either a byte half word or word When read as a byte a branch table can be used in which each entry contains one instruction branch When read as a half word each entry can contain a full...

Page 276: ...ield Reset 0000_0000_0000_0000 Figure 6 22 SIU Interrupt Vector Register SIVEC INTR Save state R3 SIVEC R4 Base of branch table lbz RX R3 0 load as byte add RX RX R4 mtsprCTR RX bctr INTR Save state R...

Page 277: ...system monitors the software watchdog period and the bus monitor timing This register can be read at any time but can be written only once after system reset MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 278: ...contains the count value of the software watchdog timer 16 23 BMT Bus monitor timing This field specifies the time out period in eight system clock resolution of the bus monitor BMT must be set to no...

Page 279: ...00E Figure 6 27 Software Service Register SWSR Table 6 16 SWSR Bit Descriptions Bits Name Description 0 15 SWSR SWT servicing sequence is written to this register To prevent SWT time out a 0x556C foll...

Page 280: ...nd SRESET do not affect this register The decrementer is powered by standby power and can continue to count when standby power is applied Decrementer counts down the time base clock and the counting i...

Page 281: ...egisters TBREF0 and TBREF1 are associated with the lower part of the time base TBL Each is a 32 bit read write register Upon a match between the contents of TBL and the reference register a maskable i...

Page 282: ...2 Keep Alive Power Registers Lock Mechanism MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field TBIRQ REFA REFB REFAE REFBE TBF TBE PORESET 0000_0000_0000_0000 Addr 0x2F C200 Figure 6 34 Time Base Co...

Page 283: ...quest Thee bits determine the interrupt priority level of the RTC Refer to Section 6 1 4 Enhanced Interrupt Controller for interrupt level encoding 8 SEC Once per second interrupt This status bit is s...

Page 284: ...egister can be read or written at any time MSB 0 LSB 31 Field ALARM Reset Unaffected Addr 0x2F C22C Figure 6 37 Real Time Clock Alarm Register RTCAL MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field...

Page 285: ...0 21 22 23 24 25 26 27 28 29 30 LSB 31 Field Reset Unaffected Figure 6 39 Periodic Interrupt Timer Count PITC Table 6 21 PITC Bit Descriptions Bits Name Description 0 15 PITC Periodic interrupt timing...

Page 286: ...eneral purpose I O pins SGPIOD 0 7 The direction input or output of this group of pins is controlled by the GDDR0 bit in the SGPIO control register 8 15 SGPIOD 8 15 SIU general purpose I O Group D 8 1...

Page 287: ...OC 0 7 The direction of SGPIOC 0 7 is controlled by 8 dedicated direction control signals SDDRC 0 7 in the SGPIO control register Each pin in this group can be configured separately as general purpose...

Page 288: ...Bits Name Description 0 7 SDDRC 0 7 SGPIO data direction for SGPIOC 0 7 Each SDDR bit zero to seven controls the direction of the corresponding SGPIOC pin zero to seven 8 15 Reserved 16 GDDR0 Group d...

Page 289: ...zed only on hard reset External soft reset initializes internal logic while maintaining system configuration The reset status register RSR reflects the most recent source to cause a reset 7 1 1 Power...

Page 290: ...data pins refer to Section 7 5 1 Hard Reset Configuration and the chip stops driving the HRESET and SRESET pins An external pull up resistor should drive the HRESET and SRESET pins high After detecti...

Page 291: ...top reset is asserted The enabled checkstop event generates an internal hard reset sequence Refer to the RCPU Reference Manual for more information 7 1 8 Debug Port Hard Reset When the development por...

Page 292: ...i e data could be corrupted Contention may occur if a write access is in progress to external memory and SRESET HRESET is asserted and the external reset configuration word RCW is used In this case th...

Page 293: ...RESET HRESET HRESET SRESET HRESET SRESET Provided only one of them is driven into the MPC561 MPC563 at a time MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS J...

Page 294: ...locked by the MFPDL bit DIVF 0 4 locked by the MFPDL bit 10 GPOR Glitch detected on PORESET pin This bit is set when the PORESET pin is asserted for more than 20ns 0 No glitch was detected on the PORE...

Page 295: ...ted and a valid NVM value exists UC3FCFIG HC 0 then the configuration is sampled from the NVM register in the UC3F module If RSTCONF is negated and no valid NVM value exists UC3FCFIG HC 1 then the con...

Page 296: ...rising edge of CLKOUT with a double buffer The setup time required for the data bus is approximately 15 cycles defined as Tsup in the following figures and the maximum rise time of HRESET should be l...

Page 297: ...ET Assertion Limp Mode Disabled Figure 7 4 Reset Configuration Timing for Short PORESET Assertion Limp Mode Enabled CLKOUT PORESET HRESET RSTCONF Internal PORESET Default RSTCONF Controlled Tsup Inter...

Page 298: ...g Requirements CLKOUT PORESET HRESET RSTCONF Internal Default RSTCONF Controlled Tsup Internal data 0 31 PLL lock PORESET CLKOUT HRESET RSTCONF DATA 1 2 3 8 9 10 11 12 13 14 15 16 Maximum time of rese...

Page 299: ...ption of Bus arbitration The default value is that internal arbitration hardware is used 0 Internal arbitration is performed 1 External arbitration is assumed 1 IP Initial Interrupt Prefix This bit de...

Page 300: ...ble 6 13 The default value is no peripheral mode enabled 17 18 SC Single Chip Select This field defines the mode of theMPC562 MPC564 See Table 6 10 00 Extended chip 32 bits data 01 Extended chip 16 bi...

Page 301: ...default state is that the internal memory map is mapped to start at address 0x0000_0000 This bit must not be high in the reset configuration word 31 DME Dual Mapping Enable This bit determines whethe...

Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...

Page 303: ...tem clock the clocks submodule provides the following TMBCLK to the time base TB and decrementer DEC PITRTCLK to the periodic interrupt timer PIT and real time clock RTC The oscillator TB DEC RTC and...

Page 304: ...1 SPLL Clock GCLK1 GCLK2 GCLK1C GCLK2C VCOOUT CLKOUT 3 1 MUX XFC TMBCLK TMBCLK Lock VDDSYN Drivers Driver Main Clock XTAL EXTAL 3 1 MUX RTC PIT Clock and Driver Oscillator MUX TBCLK 4 or 16 MODCK 1 3...

Page 305: ...MPC561 MPC563 to function with a less precise clock When operating from the backup clock the MPC561 MPC563 is in limp mode This enables the system to continue minimum functionality until the system is...

Page 306: ...se comparator The phase comparator controls the direction up or down that the charge pump drives the voltage across the external filter capacitor XFC The direction depends on whether the feedback sign...

Page 307: ...imum lock time is determined by the input clock to the phase comparator The PLL locks within 500 input clock cycles if the PLPRCR MF 4 The PLL locks within 1000 input clock cycles if PLPRCR MF 4 HRESE...

Page 308: ...et If loss of lock is detected during normal operation assertion of HRESET for example if LOLRE is set disables the PLL output clock until the lock condition is met During hard reset the STBUC bit is...

Page 309: ...or high frequency DFNH and division factor low frequency DFNL bits in SCCR are set to the value of 0 1 for DFNH and 2 for DFNL 8 5 Internal Clock Signals The internal clocks generated by the clocks mo...

Page 310: ...Figure 8 7 GCLK1_50 rises simultaneously with GCLK1 When the MPC561 MPC563 is not in gear mode the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50 EBDF determines the divis...

Page 311: ...clock is automatically selected as the time base clock source The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR When the backup clock is functioning as the syste...

Page 312: ...l bus clock GCLK2_50 is the same as CLKOUT The general system clock defaults to VCO 2 20 MHz assuming a 20 MHz system frequency with default power on reset MF values 100 101 0 1 1 1 256 16 Normal oper...

Page 313: ...m the interrupt controller This option is maskable by the PRQEN bit in the SCCR The POW bit in the MSR is clear in normal operation This option is maskable by the PRQEN bit in the SCCR When neither of...

Page 314: ...of GCLK2_50 Figure 8 6 Divided System Clocks Timing Diagram The system clocks GCLK1 and GCLK2 frequency is Therefore the complete equation for determining the system clock frequency is GCLK1 Divide by...

Page 315: ...half speed EBDF 0b01 The CLKOUT frequency system frequency defaults to VCO 2 CLKOUT can drive full half or quarter strength it can also be disabled The drive strength is controlled in the system clock...

Page 316: ...em clock to the backup clock ring oscillator BUCLK This circuit consists of a loss of clock detector which sets the LOCS status bit and LOCSS sticky bit in the PLPRCR If the LME bit in the SCCR is set...

Page 317: ...e system clock to BUCLK or PLL At PORESET negation if the PLL is not locked the loss of clock sticky bit LOCSS is asserted and the chip should operate with BUCLK hreset_b 1 b u c l k _ e n a b l e 1 a...

Page 318: ...its after the low power mode exit signal arrives There are four low power modes Doze mode Sleep mode Deep sleep mode Power down mode 8 7 1 Entering a Low Power Mode Low power modes are enabled by sett...

Page 319: ...l high 00 0 X Normal low gear 00 1 X Doze high 01 0 X Doze low 01 1 X Sleep 10 X X Deep sleep 11 X 1 Power down 11 X 0 Table 8 5 Power Mode Descriptions Operation Mode SPLL Clocks Functionality Power...

Page 320: ...s long as the TMIST is set The TMIST status bit should be cleared before entering any low power mode Table 8 7 summarizes wake up operation for each of the low power modes 8 7 3 1 Exiting from Normal...

Page 321: ...e may be up to 100 PLL input frequency clocks For a PLL input frequency of 4 MHz the wake up time is less than 125 s 8 7 3 4 Exiting from Power Down Mode Exit from power down mode is accomplished thro...

Page 322: ...ram Normal High Mode LPM 00 CSRC 0 1 Normal Low LPM 00 CSRC 1 Doze Low LPM 01 CSRC 1 Doze High LPM 01 CSRC 0 1 Sleep Mode LPM 10 CSRC 0 Deep Sleep Mode LPM 11 CSRC 0 Power Down Mode LPM 11 CSRC 0 MSR...

Page 323: ...e 50 A 1 75 mA average NOTE The power supply inputs VDD QVDDL NVDDL VDDSYN and VDDF should all be connected to the same 2 6 V power supply The KAPWR power supply can be connected to a 2 6 V standby po...

Page 324: ...5 KAPWR The oscillator time base counter decrementer periodic interrupt timer and the real time clock are fed by the KAPWR rail This allows the external power supply unit to disconnect all other sub u...

Page 325: ...n the IRAMSTBY power supply pin Run current is supplied by normal VDD IRAMSTBY must be connected to a positive power supply via a register and bypassed by a capacitor to ground see Figure 8 10 The res...

Page 326: ...e 8 12 is an example of a switching scheme for an optimized low power system SW1 and SW2 can be unified in only one switch if VDDSYN and VDD NVDDL QVDDL are supplied by the same source Clock Control P...

Page 327: ...and time base registers are powered by the KAPWR supply When the main power supply is disconnected after power down mode is entered the value stored in any of these registers is preserved If power do...

Page 328: ...riptions 0x2F C308 Time Base Reference 1 Key TBREF1K 0x2F C220 Real Time Clock Status and Control RTCSC See Table 6 19 for bit descriptions This register is locked after reset by default 0x2F C320 Rea...

Page 329: ...e 8 15 detail the power up sequencing for MPC561 MPC563 during normal operation Note that for each of the conditions detailing the voltage relationships the absolute bounds of the minimum and maximum...

Page 330: ...at a valid level before resets are negated 2 If keep alive functions are NOT used then when system power is on KAPWR QVDDL 0 1 V KAPWR 2 7 V 3 If keep alive functions ARE used then KAPWR QVDDL NVDDL...

Page 331: ...E used then KAPWR QVDDL NVDDL 2 6 V 0 1 V when system power is on KAPWR 2 6 V 0 1 V when system power is off IRAMSTBY should be powered prior to the other supplies If IRAMSTBY is powered at the same t...

Page 332: ...iption 0 DBCT Disable backup clock for timers The DBCT bit controls the timers clock source while the chip is in limp mode If DBCT is set the timers clock TMBLCK PITRCLK source will not be the backup...

Page 333: ...oftware causing the MCU to enter low power modes The MSR POW bit provides additional protection LPML is writable once after power on reset 0 LPM and CSRC bits are writable 1 LPM and CSRC bits are lock...

Page 334: ...enabled and any detection of loss of clock will switch the system clock automatically to backup clock It is also possible to switch to the backup clock by setting the STBUC bit If LME is cleared the o...

Page 335: ...H Division factor high frequency These bits determine the general system clock frequency during normal mode Changing the value of these bits does not result in a loss of lock condition These bits are...

Page 336: ...d not be modified when entering or exiting from low power mode LPM change or when back up clock is active The normal reset value for the DFNH bits is zero divide by 1 When the PLL is operating in one...

Page 337: ...upt status TMIST is set when an interrupt from the RTC PIT TB or DEC occurs The TMIST bit is cleared by writing a one to it Writing a zero has no effect on this bit The system clock frequency remains...

Page 338: ...The DIVF bits can be read and written at any time However the DIVF field can be write protected by setting the MF and pre divider lock MFPDL bit in the SCCR Changing the DIVF bits causes the SPLL to...

Page 339: ...was detected 5 VSRDE1 1 Removed on all parts that have the ZOREG bit IRAMSTBY detector disable 0 IRAMSTBY detection circuit is enabled 1 IRAMSTBY detection circuit is disabled 6 LVDRS Loss of IRAMSTB...

Page 340: ...ontrol MPC561 MPC563 Reference Manual Rev 1 2 8 38 Freescale Semiconductor 2 ZOREG is not in Rev 0 of the MPC561 but is in all later revisions It is not in Rev 0 or 0A of the MPC563 but is in Rev A an...

Page 341: ...pport Chip select and wait state generation to support peripheral or static memory devices through the memory controller Supports various memory SRAM EEPROM types synchronous and asynchronous burstabl...

Page 342: ...is not predictable however the MPC561 MPC563 always resolves the latched level to either a logic high or low before using it In addition to meeting input setup and hold times for deterministic operati...

Page 343: ...be found in subsequent subsections The buses are described in big endian manner which means that bit 0 is the most significant bit in a bus MSB and bit 31 is the least significant bit LSB ADDR 8 31 R...

Page 344: ...ent transfer is not a burst I Driven by an external master when it owns the external bus Driven low indicates that a burst transfer is in progress Driven high indicates that the current transfer is no...

Page 345: ...sfer start 1 Low O Driven by the MPC561 MPC563 when it owns the external bus Indicates the start of a transaction on the external bus I Driven by an external master when it owns the external bus It in...

Page 346: ...the bus and initiated a write transaction to an internal slave module drives DATA 0 31 Transfer Cycle Termination TA Transfer acknowledge 1 Low I Driven by the slave device to which the current trans...

Page 347: ...internal arbiter is enabled the MPC561 MPC563 asserts this signal to indicate that an external master may assume ownership of the bus and begin a bus transaction The BG signal should be qualified by...

Page 348: ...that could occur 9 5 1 Basic Transfer Protocol The basic transfer protocol defines the sequence of actions that must occur on the MPC561 MPC563 bus to perform a complete bus transaction A simplified s...

Page 349: ...ne asserted on the rising edge of the CLKOUT During a read cycle the master accepts the data bus contents as valid at the rising edge of the CLKOUT in which the TA signal is sampled asserted 9 5 2 1 S...

Page 350: ...2 9 10 Freescale Semiconductor Figure 9 5 Single Beat Read Cycle Basic Timing Zero Wait States CLKOUT ADDR 8 31 TS BR BG BB Data TA RD WR Receive bus grant and bus busy negated Assert BB drive addres...

Page 351: ...write cycle begins with a bus arbitration followed by the address transfer then the data transfer The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed t...

Page 352: ...7 Basic Flow Diagram of a Single Beat Write Cycle Master Slave 1 Request bus BR 2 Receive bus grant BG from arbiter 3 Assert bus busy BB if no other master is driving bus 4 Assert transfer start TS 5...

Page 353: ...escale Semiconductor 9 13 Figure 9 8 Single Beat Basic Write Cycle Timing Zero Wait States CLKOUT ADDR 8 31 TS BR BG BB Data TA RD WR Receive bus grant and bus busy negated Assert BB drive address and...

Page 354: ...us interface receives a small port size 16 or 8 bits indication before the transfer acknowledge to the first beat through the internal memory controller the MCU initiates successive transactions until...

Page 355: ...connecting 3 3 V devices to the E bus and performing read and write operations this mode should be invoked in order to avoid long term reliability issues of the data pads When the PDMCR2 PREDIS_EN bit...

Page 356: ...l than 3 1 volts And when one or more of the following occurs The MPC561 MPC563 uses write accesses to any external memory Data show cycles are enabled Instruction show cycles are enabled in code comp...

Page 357: ...terface Unit USIU Overview for further details The MPC561 MPC563 begins the access by supplying a starting address that points to one of the words in the array and requires the memory to sequentially...

Page 358: ...3 does not allow other unrelated master accesses or bus arbitration to intervene between the transfers 9 5 5 Burst Mechanism In addition to the standard bus signals the MPC561 MPC563 burst mechanism u...

Page 359: ...of a burst read cycle the master receives data from the addressed slave If the master needs more than one data beat it asserts BDIP Upon receiving the second to last data beat the master negates BDIP...

Page 360: ...er Acknowledge TA Receive Data 6 Drive BURST Asserted Assert BDIP BDIP Asserted Yes Return Data Assert Transfer Acknowledge TA Receive Data BDIP Asserted Yes Return Data Assert Transfer Acknowledge TA...

Page 361: ...asic Flow Diagram Of A Burst Read Cycle Figure 9 13 Burst Read Cycle 32 Bit Port Size Zero Wait State CLKOUT ADDR 8 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Val...

Page 362: ...or Figure 9 14 Burst Read Cycle 32 Bit Port Size One Wait State CLKOUT ADDR 8 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Valid is Valid is Valid Last Beat Expects...

Page 363: ...re 9 15 Burst Read Cycle 32 Bit Port Size Wait States Between Beats CLKOUT ADDR 8 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Valid is Valid is Valid Last Beat Exp...

Page 364: ...Interface MPC561 MPC563 Reference Manual Rev 1 2 9 24 Freescale Semiconductor Figure 9 16 Burst Read Cycle 16 Bit Port Size CLKOUT ADDR 8 31 TS BR BG BB Data 0 15 TA RD WR BURST TSIZ 0 1 BDIP 00 ADDR...

Page 365: ...dge TA Drive Data 6 Drive BURST Asserted Assert BDIP BDIP Asserted Yes Sample Data Assert Transfer Acknowledge TA Drive Data BDIP Asserted Yes Sample Data Assert Transfer Acknowledge TA Drive Data BDI...

Page 366: ...ernal master Figure 9 18 Burst Write Cycle 32 Bit Port Size Zero Wait States Only for External Master Memory Controller Service Support ADDR 8 31 MTS BR1 BG1 BB1 RD WR1 BURST1 TSIZ 0 1 BDIP1 Data Data...

Page 367: ...and BDIP will be asserted for one cycle if the RCPU core requests a burst but the USIU splits it into a sequence of normal cycles Figure 9 19 Burst Inhibit Read Cycle 32 Bit Port Size Emulated Burst C...

Page 368: ...61 MPC563 Reference Manual Rev 1 2 9 28 Freescale Semiconductor Figure 9 20 Non Wrap Burst with Three Beats CLKOUT ADDR 0 29 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP 00 BI ADDR 30 31 n n modulo 4...

Page 369: ...nment and Packaging of Transfers The MPC561 MPC563 external bus requires natural address alignment Byte accesses allow any address alignment Half word accesses require address bit 31 to equal zero CLK...

Page 370: ...TA 0 15 and an 8 bit port must reside on DATA 0 7 The MPC561 MPC563 always tries to transfer the maximum amount of data on all bus cycles For a word operation it always assumes that the port is 32 bit...

Page 371: ...uirements For Read Cycles Transfer Size TSIZE 0 1 Address 32 bit Port Size 16 bit Port Size 8 bit Port Size ADDR 30 31 DATA 0 7 DATA 8 15 DATA 16 23 DATA 24 31 DATA 0 7 DATA 8 15 DATA 0 7 Byte 01 00 O...

Page 372: ...s grant BG and bus busy BB signals The device that needs the bus asserts BR The device then waits for the arbiter to assert BG In addition the new master must look at BB to ensure that no other master...

Page 373: ...be driven by the external bus master 9 5 7 2 Bus Grant The arbiter asserts BG to indicate that the bus is granted to the requesting device This signal can be negated following the negation of BR or k...

Page 374: ...until the transfer is complete To avoid contention on the BB line the master should three state this signal when it gets a logical one value This requires the connection of an external pull up resist...

Page 375: ...ting for BG from the arbiter The priority of the external device relative to the internal MPC561 MPC563 bus masters is programmed in the SIU module configuration register If the external device reques...

Page 376: ...the internal bus without requesting it first in order to improve performance Internal external 0 Instruction access Internal external 3 Data access Internal external 4 External access external externa...

Page 377: ...aster drives it Refer to Figure 9 25 9 5 8 2 Address Bus The address bus consists of 32 bits with ADDR0 the most significant bit and ADDR31 the least significant bit Only 24 bits ADDR 8 31 are availab...

Page 378: ...as either a normal or alternate master cycle user or supervisor and instruction or data type The address type signals are valid at the rising edge of the clock in which the special transfer start STS...

Page 379: ...ervisor mode 1 1 1 RCPU normal instruction supervisor mode 1 0 1 0 RCPU reservation data supervisor mode 1 1 1 RCPU normal data supervisor mode 1 0 0 0 1 RCPU normal instruction program trace user mod...

Page 380: ...multiple cycles and increment the address for the slave to complete the burst transfer For a system that does not use the burst mode at all this signal can be tied low permanently Refer to Section 10...

Page 381: ...Termination Signals Protocol Timing Diagram External Bus MCU Slave 2 Slave 1 Acknowledge Signals TA TEA CLKOUT ADDR 8 31 TS TA BI TEA RD WR TSIZ 0 1 Slave 1 Slave 2 Slave 1 allowed to drive acknowled...

Page 382: ...us to every MPC500 master The storage reservation protocol makes the following assumptions Each processor has at most one reservation flag lwarx sets the reservation flag lwarx by the same processor c...

Page 383: ...ng a bus cycle initiated by the RCPU stwcx instruction If the reservation flag is set the EBI begins with the bus cycle If the reservation flag is reset no bus cycle is initiated externally and this s...

Page 384: ...s a memory cycle to the previously reserved address located in the remote bus as a result of an stwcx instruction the following two cases can occur If the reservation flag is set the buses interface a...

Page 385: ...pen drain pin that allows the wired or of any different sources of error generation 9 5 11 1 Retrying a Bus Cycle When an external device asserts the RETRY signal during a bus cycle the MPC561 MPC563...

Page 386: ...63 Reference Manual Rev 1 2 9 46 Freescale Semiconductor Figure 9 32 Retry Transfer Timing Internal Arbiter CLKOUT ADDR 8 31 TS BR BG output BB Data TA RD WR BURST TSIZ 0 1 RETRY input ADDR ADDR Allow...

Page 387: ...nation only if it detects it before the first data beat was acknowledged by the slave device When the RETRY signal is asserted as a termination signal on any data beat of the access after the first be...

Page 388: ...e 16 byte transfer recognizes the RETRY signal assertion as a transfer error acknowledge In the case in which a small port size causes the MPC561 MPC563 to break a bus transaction into several small t...

Page 389: ...ollowings outputs TA TEA or RETRY If the access completes successfully the MPC561 MPC563 asserts TA and the external master can proceed with another external master access or relinquish the bus If an...

Page 390: ...nal Master 1 Request Bus BR 2 Receives Bus Grant BG From Arbiter 3 Asserts Bus Busy BB if No Other Master is Driving 4 Assert Transfer Start TS 1 Receives Address 1 Returns Data 1 Asserts Transfer Ack...

Page 391: ...minimum number of wait states for such access is two clocks The accesses in these figures are valid for both peripheral mode and slave mode External Master 1 Asserts Transfer Acknowledge TA Address i...

Page 392: ...Peripheral Mode External Master Reads from MPC561 MPC563 Two Wait States CLKOUT ADDR 8 31 TS input BR input BG BB Data TA output RD WR Receive Bus Grant and Bus Busy Negated Assert BB Drive Address an...

Page 393: ...ernal to external access to be executed The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock Figure 9 39 describes...

Page 394: ...Driving 4 Assert Transfer Start TS 5 Drives Address and Attributes 1 Receives Address 1 Returns Data 1 Asserts Transfer Acknowledge TA 1 Receives Data Address in Internal Memory Map No Yes Asserts CS...

Page 395: ...urposes A show cycle can have one address phase and one data phase or just an address phase in the case of instruction show cycles The cycle can be a write or a read access The data for both the read...

Page 396: ...le transaction encodings Instruction show cycle bus transactions have the following characteristics see Figure 9 41 One clock cycle Address phase only in decompression on mode part of the compressed a...

Page 397: ...he following characteristics see Figure 9 42 Two clock cycle duration Address valid for two clock cycles Data is valid only in the second clock cycle STS signal only is asserted no TA or TS CLKOUT ADD...

Page 398: ...nual Rev 1 2 9 58 Freescale Semiconductor Figure 9 42 Data Show Cycle Transaction CLKOUT ADDR 8 31 BR in BG out BB Data TA RD WR BURST TSIZ 0 1 ADDR1 ADDR2 STS TS DATA1 DATA2 Read Data Show Cycle Bus...

Page 399: ...he memory controller takes ownership of the external signals and controls the access until its termination Refer to Figure 10 1 Figure 10 1 Memory Controller Function within the USIU 10 1 Overview The...

Page 400: ...tion The address type comparison occurs with a mask option as well From 0 to 30 wait states can be programmed with TA generation Four write enable and byte enable signals WE BE 0 3 are available for e...

Page 401: ...ure The memory controller consists of a basic machine that handles the memory access cycle the general purpose chip select machine GPCM When any of the internal masters request a new access to externa...

Page 402: ...EEPROM Array 10 2 1 Associated Registers Status bits for each memory bank are found in the memory control status register MSTAT The MSTAT reports write protect violations for all the banks Each of the...

Page 403: ...o control the memory access If a match is found in more than one bank the lowest bank matched handles the memory access e g bank zero is selected over bank one NOTE When an external master accesses a...

Page 404: ...however an external burst access with reduced data setup time will corrupt a load store to any USIU register The reduced setup time mode may or may not have a performance impact depending on the prope...

Page 405: ...or 10 7 10 2 6 2 Case 2 Short Setup Time Initial access Enabling short setup time requires one clock cycle The number of clocks required therefore 4 clocks are required Initial access time of memory D...

Page 406: ...ry of Short Setup Time With normal setup time and a 4 beat burst a 4 2 2 2 burst cycle is required which is reduced to a 4 1 1 1 burst cycle with a short setup time Short setup time creates a saving o...

Page 407: ...5 A 4 2 2 2 Burst Read Cycle One Wait State Between Bursts CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP 00 ADDR 28 31 0b0000 Normal Late Last Beat No Data Expected Expects Another Da...

Page 408: ...a 4 1 1 1 cycle 10 3 Chip Select Timing The general purpose chip select machine GPCM allows a glueless and flexible interface between the MPC561 MPC563 and external SRAM EPROM EEPROM ROM peripherals W...

Page 409: ...pired this assertion terminates the memory cycle When SETA is cleared it is forbidden to assert external TA less than two clocks before the wait states counter expires Table 10 2 Timing Attributes Sum...

Page 410: ...the memory device where each WE BE line corresponds to a different data byte Figure 10 7 GPCM Memory Devices Interface In Figure 10 8 the CSx timing is the same as that of the address lines output The...

Page 411: ...Peripheral Devices Interface Example Figure 10 9 illustrates the basic connection between the MPC561 MPC563 and an external peripheral device In this case CSx is connected directly to the chip enable...

Page 412: ...n TRLX is set and ACS 0b00 the memory controller inserts an additional cycle between address and strobes CS line and WE OE When TRLX and CSNT are both set in a write to memory the strobe lines WE BE 0...

Page 413: ...10 12 through Figure 10 14 are examples of write accesses using relaxed timing In Figure 10 12 note the following points Because TRLX is set assertion of the CS and WE strobes is delayed by one clock...

Page 414: ...y one clock cycle Because ACS 11 the assertion of CS is delayed an additional half clock cycle Because CSNT 1 WE is negated one clock cycle earlier than normal Refer to Figure 10 8 The total cycle len...

Page 415: ...f the CS and WE strobes Because CSNT 1 WE BE is negated one clock cycle earlier than normal Refer to Figure 10 8 CS is not negated one clock cycle earlier since ACS 00 The total cycle length is three...

Page 416: ...responding OR register can be set In this case any MPC561 MPC563 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access...

Page 417: ...tive Accesses Write After Read EHTR 0 Figure 10 16 shows a write access following a read access when EHTR 1 An extra clock is inserted between the cycles For a write cycle following a read this is tru...

Page 418: ...16 Consecutive Accesses Write After Read EHTR 1 Figure 10 17 shows consecutive accesses from different banks Because EHTR 1 and the accesses are to different banks an extra clock cycle is inserted Clo...

Page 419: ...Banks EHTR 1 Figure 10 18 shows two consecutive read cycles from the same bank Even though EHTR 1 no extra clock cycle is inserted between the memory cycles In the case of two consecutive read cycles...

Page 420: ...or OE Asserted WE BE Negated to Add Data Invalid OE Negated to Add Data Invalid Total Number of Cycles 0 read 00 X 0 1 4 clock 3 4 clock X 1 4 clock 2 SCY 0 read 10 X 1 4 clock 1 4 clock 3 4 clock X 1...

Page 421: ...ll as Section 9 5 5 Burst Mechanism NOTE The LBDIP TBDIP function can operate only when the cycle termination is internal using the number of wait states programmed in one of the ORx registers The LBD...

Page 422: ...ead cycle The lower write read enable WE3 BE3 indicates that the lower eight bits of the data bus contains valid data during a write cycle The write byte enable lines affected in a transaction for 32...

Page 423: ...ich is also mapped into one of the four regions available in the memory controller If code or data is written to the dual mapped region care must be taken to avoid overwriting this code or data by nor...

Page 424: ...should be taken to change the dual mapping setup before the first data access Dual mapping is not supported for an external master when the memory controller serves the access in such a case the MPC56...

Page 425: ...s after this write provided the preferred address range is first loaded into the chip select base register BRx After the first write to ORx the global chip select can only be restarted with a system r...

Page 426: ...ve device A synchronous master initiates a transfer by asserting TS The ADDR 0 31 signals must be stable from the rising edge of CLKOUT during which TS is sampled until the last TA acknowledges the tr...

Page 427: ...l master s address correctly To activate this feature the MTSC bit must be set in the SIUMCR register Use external logic to control devices that can have burst accesses from an external master On the...

Page 428: ...ster Basic Access GPCM Controlled NOTE Because the MPC561 MPC563 has only 24 address signals the eight most significant internal address lines are driven as 0b0000_0000 and so compared in the memory c...

Page 429: ...tra cycles to complete an access to a smaller port size device as it does not own the external bus 3 When the SETA bit in the base register is set then the timing programming for the various strobes C...

Page 430: ...ding to TEA assertion will if enabled prompt the read of this register if TA is not asserted during a write cycle WPERx is cleared by writing one to the bit or by performing a system reset Writing a z...

Page 431: ...A signal to be asserted by the bus monitor logic if enabled causing termination of this cycle 0 Both read and write accesses are allowed 1 Only read accesses are allowed The CSx signal and TA are not...

Page 432: ...bit is set NOTE An access to a region that has no V bit set may cause a bus monitor timeout See Table 10 9 for the reset value of this bit in BR0 Table 10 9 BRx V Reset Value Branch Register BRx V Re...

Page 433: ...g a system reset the CSNT bit is reset in OR0 0 CS WE are negated normally 1 CS WE are negated a quarter of a clock earlier than normal Following a system reset the CSNT bit is cleared in OR0 21 22 AC...

Page 434: ...to this memory region Relaxed timing multiplies by two the number of wait states determined by the SCY and BSCY fields Refer to Section 10 3 5 Summary of GPCM Timing Options for a full list of the ef...

Page 435: ...3 1xx Reserved 31 DME Dual mapping enabled This bit indicates that the contents of the dual mapping registers and associated base and option registers are valid and enables the dual mapping operation...

Page 436: ...in any order in the field allowing a resource to reside in more than one area of the address map This field can be read or written at any time 7 9 Reserved 10 12 ATM Address type mask This field can b...

Page 437: ...ter and slave on U bus Does not start two back to back accesses on the U bus Supports U bus pipelining Retries back to back accesses from U bus masters Non pipelined master and slave on the L bus Gene...

Page 438: ...ed attribute Interrupt generated upon Access violation Load from guarded region Write to read only region The MSR DR bit data relocate controls DMPU protection on off operation Programming is done usi...

Page 439: ...ational and there is no external master access to the U bus Slave mode enables an external master to access any internal bus slave while the RCPU is fully operational The L2U transfers load store acce...

Page 440: ...2U control registers are initialized to their reset states The L2U also drives the reset configuration word from the U bus to the L bus upon hard reset 11 4 3 Peripheral Mode In the peripheral mode of...

Page 441: ...Ax RS sets a match indication When more than one match indication occurs the effective region is the region with the highest priority Priority is determined by region number highest priority correspon...

Page 442: ...cle until either the access is not speculative or it is canceled by the RCPU Core NOTE The programmer must not overlap the CALRAM memory space with any enabled region Overlapping an enabled region wit...

Page 443: ...on logic For consistency all storage access violations have the same termination result Thus access violations for load store accesses started by the RCPU always have the same termination from all sla...

Page 444: ...e request by another master will clear the reservation flag A load with reservation request by the RPCU updates the reservation address related to a previous load with reservation request and sets the...

Page 445: ...e visible to the external bus L bus show cycles are software controlled Table 11 2 Reservation Snoop Support Reserved Location On Intruding Alternate Master Action Taken on stwcx cycle L bus L master...

Page 446: ...ks for the complete process A retried access on the L bus no address acknowledge that qualifies to be show cycled will be accepted when it is actually acknowledged This will cause a 1 clock delay befo...

Page 447: ...the U bus access asserting the show cycle request on the U bus along with address attributes The L2U module provides address recognition acknowledgment for the address phase If the no show cycle indi...

Page 448: ...tion LB AACK LB ABORT Comments 1 L bus Slave1 1 L bus slave includes all address in the L bus address space No X2 2 X indicates don t care conditions Not show cycled Cycle will be retried one clock la...

Page 449: ...l mode There is no MPC500 instruction to access either a half word or a byte of the special purpose register All L2U registers are only word accessible read and write in peripheral mode A half word or...

Page 450: ...rotect the CALRAM on the L bus from U bus accesses Any attempt to set or clear the SP bit from the U bus side has no affect Once this bit is set the L2U blocks all CALRAM accesses initiated by the U b...

Page 451: ...the corresponding block size attribute specified in the region attribute register L2U_RAx 20 31 Reserved MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field RS Reset 0000_0000_0000_0000 16 17 18 19 20 21...

Page 452: ...read write access 22 24 Reserved 25 G Guarded attribute 0 Not guarded from speculative accesses 1 Guarded from speculative accesses 26 31 Reserved MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field ENR0...

Page 453: ...Protection bits 00 No supervisor access no user access 01 Supervisor read write access no user access 10 Supervisor read write access user read only access 11 Supervisor read write access user read wr...

Page 454: ...L Bus to U Bus Interface L2U MPC561 MPC563 Reference Manual Rev 1 2 11 18 Freescale Semiconductor...

Page 455: ...ultiplexer Interrupt synchronizer Clock control Scan control 12 1 Features Provides complete interfacing between the U bus and the IMB3 15 bits 32 Kbytes of address decode on IMB3 32 bit data bus Read...

Page 456: ...uration register UMCR If the STOP 1 the IMB3 clock is not generated If the STOP 0 and the HSPEED 0 the IMB3 clock is generated as the inversion of the internal system clock This is the same frequency...

Page 457: ...to the interrupt controller in the USIU through the UIMB interface The UIMB interrupt synchronizer latches the interrupts from the modules on the IMB3 and drives them onto the U bus where they are la...

Page 458: ...LBS signals continuously incrementing through a code sequence 0b00 0b01 0b10 0b11 once every clock The UMCR IRQMUX bits in the IMB3 module configuration register select which type of multiplexing the...

Page 459: ...rrupt controller in the USIU If IMB3 modules drive interrupts on any of the 24 levels levels eight through 31 they will be latched in UIPEND in the UIMB If any of the register bits 7 to 31 are set the...

Page 460: ...ws the implementation of the interrupt synchronizer Figure 12 6 Interrupt Synchronizer Block Diagram 12 5 Programming Model Table 12 5 lists the registers used for configuring and testing the UIMB mod...

Page 461: ...nfiguration Register UMCR The UIMB module configuration register UMCR is accessible in supervisor mode only S T 0x30 7F90 UIMB Test Control Register UTSTCREG Reserved 0x30 7F94 0x30 7F9F Reserved S 0x...

Page 462: ...tiplexing of the 32 possible interrupt requests onto the eight IMB3 interrupt request lines 00 Disables the multiplexing scheme on the interrupt controller within this interface What this means is tha...

Page 463: ...30 7FA0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field LVL 16 LVL 17 LVL 18 LVL 19 LVL 20 LVL 21 LVL 22 LVL 23 LVL 24 LVL 25 LVL 26 LVL 27 LVL 28 LVL 29 LVL 30 LVL 31 HRESET 0000_0000_0000_...

Page 464: ...U Bus to IMB3 Bus Interface UIMB MPC561 MPC563 Reference Manual Rev 1 2 12 10 Freescale Semiconductor...

Page 465: ...lity in enhanced mode For this revision of the QADC the name QADC64E implies the enhanced version of the QADC module not just enhanced mode of operation For simplicity the names QADC and QADC64E may b...

Page 466: ...omated queue modes initiated by External edge trigger Periodic Interval timer within QADC64E module Software command External gated trigger Queue 1 only Single scan or continuous scan of queues 64 res...

Page 467: ...starting at 0x30 4C00 QADC64E B occupies 0x30 4C00 to 0x30 4FFF Z Table 13 1 QADC64E_A Address Map Address MSB LSB Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4800 STOP FRZ LOC K FLI P SUPV Mo...

Page 468: ...ation register enables Table 13 2 QADC64E_B Address Map Address MSB LSB Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4C00 STO P FRZ LOC K FLI P SUPV Module Config 1 1 Registers are accessible o...

Page 469: ...ord table Figure 13 2 QADC64E Conversion Queue Operation 13 2 5 External Multiplexing The QADC can use from one to four 8 input external multiplexer chips to expand the number of analog signals that m...

Page 470: ...epresent eight analog input channels The QADC converts the proper input channel ANw ANx ANy ANz by interpreting the channel number in the CCW Refer to Table 13 3 Figure 13 3 Example of External Multip...

Page 471: ...p and Table 13 2 for the QADC64E_B address map See Section 13 3 1 4 Supervisor Unrestricted Address Space for access modes of these registers The remaining five registers in the control register block...

Page 472: ...ck that operating mode MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field STOP FRZ LOCK FLIP SUPV SRESET 0000_0000 1 000_0000 Addr 0x30 4800 QADCMCR_A 0x30 4C00 QADCMCR_B Figure 13 4 Module Configura...

Page 473: ...the periodic interval timer is held in reset during stop mode If the STOP bit is clear stop mode is disabled 13 3 1 2 Freeze Mode Freeze mode occurs when the background debug mode is enabled in the US...

Page 474: ...of Operation The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E modules Out of reset the QADC64E modules are in legacy mode FLIP 0 and the LOCK bit is clear indi...

Page 475: ...d Attempts to write unimplemented data space in the unrestricted access mode and SUPV 1 causes the bus master to assert a bus error condition and no data is written In all other attempts to write unim...

Page 476: ...is driven during the time multiplexed bus during one of four different time slots with eight levels communicated per time slot No hardware priority is assigned to interrupts Furthermore if more than o...

Page 477: ...e digital input only signals Digital input signal states are read from the 8 bit PORTQB register Port B can also be used as non multiplexed analog inputs AN 51 48 and AN 3 0 and external multiplexer a...

Page 478: ...0 output signals The MA 2 0 signals are forced to be digital outputs regardless of the data direction setting and the multiplexed address outputs are driven The data returned during a port data regis...

Page 479: ...C0A QACR0_B Figure 13 9 Control Register 0 QACR0 Table 13 9 QACR0 Bit Descriptions Bits Name Description 0 EMUX Externally multiplexed mode The EMUX bit configures the QADC64E for externally multiplex...

Page 480: ...of queue 1 to start after a trigger event occurs The SSE1 bit may be set to a one during the same write cycle when the MQ1 bits are set for one of the single scan queue operating modes The single scan...

Page 481: ...110 Interval timer single scan mode time QCLK period x 217 01111 External gated single scan mode started with SSE1 10000 Reserved mode 10001 Software triggered continuous scan mode 10010 External trig...

Page 482: ...pause interrupt associated with queue 2 1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2 which has the pause bit set 2 SSE2 Queue 2 Single Scan Enable Bit SSE2 en...

Page 483: ...5 the second sequence starts at CCW16 with a pause after CCW17 and an EOQ programmed in CCW39 With BQ2 set to CCW10 and the continuous scan mode selected queue execution begins When the pause is encou...

Page 484: ...me QCLK period x 214 01100 Interval timer single scan mode time QCLK period x 215 01101 Interval timer single scan mode time QCLK period x 216 01110 Interval timer single scan mode time QCLK period x...

Page 485: ...CW in the location prior to that pointed to by BQ2 when the current CCW contains an end of queue code instead of a valid channel number or when the currently completed CCW is in the last location of t...

Page 486: ...n mode the pause flag will not set and execution continues without pausing This has allowed for the added definition of PF1 in the external gated modes PF1 is maintained by the QADC64E regardless of w...

Page 487: ...all scan modes 4 TOR1 Queue 1 Trigger Overrun TOR1 indicates that an unexpected trigger event has occurred for queue 1 TOR1 can be set only while queue 1 is in the active state A trigger event generat...

Page 488: ...6 shows the bits in the QS field and how they affect the status of queue 1 and queue 2 Refer to Section 13 6 Trigger and Queue Interaction Examples which shows the 4 bit queue status field transitions...

Page 489: ...terval Timer Trigger Single scan Pauses Yes Periodic Interval Timer Continuous scan Pauses Yes Software Initiated Single scan Continues Yes Software Initiated Continuous scan Continues Yes External Ga...

Page 490: ...trigger pending when a trigger event occurs for queue 2 while queue 1 is active In the opposite case when a trigger event occurs for queue 1 while queue 2 is active queue 2 is aborted and the status i...

Page 491: ...to know what CCW was last completed for queue 1 This field is a software read only field and write operations have no effect CWPQ1 allows software to read the last executed CCW in queue 1 regardless o...

Page 492: ...ons The software also establishes the criteria for initiating the queue execution by programming the queue operating mode The queue operating mode determines what type of trigger event causes queue ex...

Page 493: ...se bit is found in a CCW When the pause bit is set in the current CCW the QADC64E stops execution of the queue until a new trigger event occurs The pause status flag bit is set which may cause an inte...

Page 494: ...ZE line is asserted the QADC64E freezes at the end of the conversion in progress When internal FREEZE is negated the QADC64E resumes queue execution beginning with the next CCW entry Refer to Section...

Page 495: ...the queue Channels 60 to 62 are special internal channels When one of these channels is selected the sample amplifier is not used The value of VRL VRH or VRH VRL 2 is placed directly into the convert...

Page 496: ...A7 AN58 AN59 VRL VRH I O I O I I 111010 111011 111100 111101 58 59 60 61 VRH VRL 2 End of Queue Code 111110 111111 62 63 Table 13 20 Multiplexed Channel Assignments and Signal Designations Multiplexed...

Page 497: ...ite operations to the result word table are right justified The three result data formats are produced by routing the RAM bits onto the data bus The software chooses among the three formats by reading...

Page 498: ...subsystem which includes the front end analog multiplexer and analog to digital converter 13 4 1 Analog to Digital Converter Operation The analog subsystem consists of the path from the input signals...

Page 499: ...7 s with a 2 0 MHz QCLK If the maximum final sample time period of 16 QCLKs is selected the total conversion time is 28 QCLKs or 14 s with a 2 0 MHz QCLK Figure 13 21 illustrates the timing for conve...

Page 500: ...al to accuracy The input voltage is buffered onto the sample capacitor to reduce crosstalk between channels 13 4 4 Digital to Analog Converter DAC Array The digital to analog converter DAC array consi...

Page 501: ...ert START CONV signal indicates to the A D converter that the desired channel has been sent to the MUX IST indicates the desired sample time BYP indicates whether to bypass the sample amplifier The en...

Page 502: ...queue 1 the current queue 2 conversion is aborted The status register reports the queue 2 status as suspended Any trigger events occurring for queue 2 while queue 2 is suspended are captured as trigg...

Page 503: ...es The choice of single scan or continuous scan applies to the full queue and is not applied to each sub queue Once a sub queue is initiated each CCW is executed sequentially until the last CCW in the...

Page 504: ...he end of queue condition is recognized the completion flag is set and the queue becomes idle A conversion is not performed BQ2 is set beyond the end of the CCW table 64 127 and a trigger event occurs...

Page 505: ...Single scan modes Software initiated single scan mode External trigger single scan mode External gated single scan mode Periodic Interval timer single scan mode Continuous scan modes Software initiate...

Page 506: ...queue The single scan enable bit remains set until the queue is completed After the queue reaches completion the QADC64E resets the single scan enable bit to zero If the single scan enable bit is wri...

Page 507: ...edge The external trigger single scan mode is useful when the input trigger rate can exceed the queue execution rate Analog samples can be taken in sync with an external event even though the softwar...

Page 508: ...scan of the queue to be initiated by the periodic interval timer The periodic interval timer generates a trigger event whenever the time interval elapses The trigger event may cause the queue executi...

Page 509: ...ing EOQ code channel 63 the last queue conversion to the first queue conversion requires 1 additional CCW fetch cycle Therefore continuous samples are not coherent at this boundary In addition the tim...

Page 510: ...tion to continue from the paused state Some applications need to synchronize the sampling of analog channels to external events There are cases when it is not possible to use software initiation of th...

Page 511: ...he first CCW in the queue The periodic interval timer generates a trigger event whenever the time interval elapses The trigger event may cause the queue execution to continue following a pause or queu...

Page 512: ...its the frequency of QCLK to be software selectable It also allows the duty cycle of the QCLK waveform to be programmable The software establishes the basic high phase of the QCLK waveform with the PS...

Page 513: ...K Time PSH 1 fSYS Low QCLK Time PSL 1 fSYS FQCLK 1 High QCLK Time Low QCLK Time Where PSH 0 to 31 the prescaler QCLK high cycles in QACR0 PSL 0 to 7 the prescaler QCLK low cycles in QACR0 fSYS IMB3 cl...

Page 514: ...bit PSL field selects the number of IMB3 clock cycles in the low phase of the QCLK wave Example 1 in Table 13 21 shows that when the PSH 19 the QCLK remains high for 20 cycles if the IMB3 clock and wi...

Page 515: ...top mode causes QACR1 and QACR2 to be reset to zero a valid periodic or interval timer mode must be written after stop mode is exited to release the timer from reset When the IMB3 internal FREEZE line...

Page 516: ...orts 8 bit 16 bit and 32 bit data transfers at even and odd addresses Coherency of results read ensuring that all results read were taken consecutively in one scan is not guaranteed For example if a r...

Page 517: ...16 bits of data is written to and read from the QADC64E location with each access 16 bit accesses to an odd address require two bus cycles one byte of two different 16 bit QADC64E locations is access...

Page 518: ...igger events that are intended to initiate conversions and they can occur asynchronously in relation to each other and other conversions in progress For example a queue can be idle awaiting a trigger...

Page 519: ...not shown because they exist only very briefly between stable status conditions The first three examples in Figure 13 27 through Figure 13 29 S1 S2 and S3 show what happens when a new trigger event is...

Page 520: ...ion of the previous queue leaving software little time to retrieve the previous results Also when trigger events are occurring at a high rate for queue 1 the lower priority queue 2 channels may not ge...

Page 521: ...Situation S5 Figure 13 31 shows that when multiple queue 2 trigger events are detected while queue 1 is busy the trigger overrun error bit is set but queue 1 execution is not disturbed Situation S5 al...

Page 522: ...omplete so that queue 1 execution can begin Queue 2 is considered suspended After queue 1 is finished queue 2 starts over with the first CCW when the RES resume control bit is set to 0 Situation S7 Fi...

Page 523: ...s execution with the aborted CCW not the first CCW in the queue Figure 13 34 CCW Priority Situation 8 QADC S7 T1 T1 PAUSE Q1 Q2 QS IDLE IDLE IDLE 0010 0110 1010 0010 ACTIVE 0000 IDLE Q1 PF1 C1 C2 0000...

Page 524: ...rmits the software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being lost Figure 13 36 CCW Priority Situation 10 QADC S9 T1 PAUSE Q1 Q2 QS IDLE IDLE ACT IDLE...

Page 525: ...ogress unlike queue 1 suspending queue 2 After the freeze condition is removed the QADC64E continues queue execution with the next CCW in sequence Trigger events that occur during freeze are not captu...

Page 526: ...13 40 CCW Freeze Situation 14 Figure 13 41 CCW Freeze Situation 15 Figure 13 42 CCW Freeze Situation 16 QADC S13 C1 C2 T2 Q2 CF2 C3 C4 FREEZE QADC S14 C1 C2 T1 Q1 CF1 C3 C4 FREEZE T1 T1 T2 T2 TRIGGER...

Page 527: ...examples Example 1 below shows the timing for basic conversions where the following is assumed Q1 begins with CCW0 and ends with CCW3 CCW0 has pause bit set CCW1 does not have pause bit set External...

Page 528: ...pause bit is set CCW0 please note that CWP does not increment until triggered When the pause is not set CCW1 the CWP increments with EOC The conversion results Q1 RES x show the result associated with...

Page 529: ...eflect the condition that a gate closing occurred before the queue completed is a proposal under consideration at this time as example 2 NOTE At the end of Q1 the completion flag CF1 sets and the queu...

Page 530: ...ls can be configured as digital input or digital output signals and Port B signals can be used as 8 bit digital input signals Port A signals are referred to as PQA 7 0 when used as a bidirectional 8 b...

Page 531: ...ut Signals The QADC64E uses two external trigger signals ETRIG 2 1 Each of the two input external trigger signals is associated with one of the scan queues queue 1 or queue 2 The assignment of ETRIG 2...

Page 532: ...SSA and the sample amplifier has accurately transferred the input signal resolution is ratiometric within the limits defined by VRL and VRH If VRH is greater than VDDA the sample amplifier can never t...

Page 533: ...ived from a common regulator filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned For example an RC low pass filter could be used to isolate the...

Page 534: ...proach is to star point the different grounds at the power supply origin thus keeping the ground isolated Refer to Figure 13 51 Another approach is to star point the different grounds near the analog...

Page 535: ...capacitive bypassing may sufficed In extreme cases inductors or ferrite beads may be necessary if noise or RF energy is present Series resistance is not advisable since there is an effective DC curren...

Page 536: ...ide the QADC64E Figure 13 52 Electrical Model of an A D Input Signal In Figure 13 52 RF RSRC and CF comprise the external filter circuit CP is the internal parasitic capacitor CSAMP is the capacitor a...

Page 537: ...tions The source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not Figure 13 53 shows the connection of eig...

Page 538: ...MC54HC4051 MC74HC4051 MC54HC4052 MC74HC4052 MC54HC4053 etc RSOURCE2 CFILTER CSOURCE RFILTER2 C MUXIN RSOURCE2 CFILTER C SOURCE RFILTER2 C MUXIN RSOURCE2 CFILTER CSOURCE RFILTER2 C MUXIN RSOURCE2 CFIL...

Page 539: ...g The external circuit described in Table 13 24 is a low pass filter A user interested in measuring an AC component of the external signal must take the characteristics of this filter into account 13...

Page 540: ...currents into or out of the input Refer to Appendix F Electrical Characteristics to for more information on exact magnitudes Either stress condition can potentially disrupt conversion results on neigh...

Page 541: ...channel RSELECTED Source impedance on channel selected for conversion The current into IIN the neighboring signal is determined by the KN current coupling ratio of the parasitic bipolar transistor KN...

Page 542: ...QADC64E Legacy Mode Operation MPC561 MPC563 Reference Manual Rev 1 2 13 78 Freescale Semiconductor...

Page 543: ...y mode For this revision of the QADC the name QADC64E implies the enhanced version of the QADC64 module not just enhanced mode of operation For simplicity the names QADC and QADC64E may be used interc...

Page 544: ...ernal edge trigger Periodic Interval timer within QADC64E module Software command External gated trigger queue 1 only Single scan or continuous scan of queues 64 result registers in each QADC64E modul...

Page 545: ...ing at 0x30 4C00 QADC64E_B occupies 0x30 4C00 to 0x30 4FFF Table 14 1 QADC64E_A Address Map Address MSB LSB Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4800 STOP FRZ LOC K FLI P SUP V Module C...

Page 546: ...y a series of writes Table 14 2 QADC64E_B Address Map Address MSB LSB Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30 4C00 STOP FRZ LOC K FLI P SUPV Module Config 1 1 Registers are accessible only...

Page 547: ...rnal Multiplexing The QADC can use from one to four 8 input external multiplexer chips to expand the number of analog signals that may be converted The externally multiplexed channels are automaticall...

Page 548: ...B and each one can represent eight analog input channels The QADC converts the proper input channel ANw ANx ANy ANz by interpreting the channel number in the CCW Refer to Table 14 3 Figure 14 3 Exampl...

Page 549: ...ning five registers in the control register block control the operation of the queuing mechanism and provide a means of monitoring the operation of the QADC64E Control register 0 QACR0 contains hardwa...

Page 550: ...n 0 STOP Stop Enable Refer to Section 14 3 1 1 Low Power Stop Mode for more information 0 Disable stop mode 1 Enable stop mode 1 FRZ Freeze Enable Refer to Section 14 3 1 2 Freeze Mode for more inform...

Page 551: ...ed there are three possible queue freeze scenarios When a queue is not executing the QADC64E freezes immediately When a queue is executing the QADC64E completes the conversion in progress and then fre...

Page 552: ...mitted only when the software is operating in supervisor access mode Assignable data space can be either restricted to supervisor only access or unrestricted to both supervisor and user data space acc...

Page 553: ...TEST The supervisor unrestricted space designation for the CCW table the result word table and the remaining QADC64E registers is programmable 14 3 2 QADC64E Interrupt Register QADCINT specifies the p...

Page 554: ...Levels on IRQ with ILBS 14 3 3 Port Data Register QADC64E ports A and B are accessed through two 8 bit port data registers PORTQA and PORTQB MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field IRL1 I...

Page 555: ...rresponding bit in the data direction register defines the signal to be an input When the data direction bit specifies the signal to be an output the content of the port data register is read PORTQA a...

Page 556: ...f the data direction setting and the multiplexed address outputs are driven The data returned during a port data register read is the value of the multiplexed address latches which drive MA 2 0 regard...

Page 557: ...r to Appendix F Electrical Characteristics for more information on the QADC64E operating clock frequency fQCLK values fQCLK can range from 2 to 128 system clock cycles fSYSCLK To keep fQCLK within the...

Page 558: ...3 1110010 115 0010011 20 0110011 52 1010011 84 1110011 116 0010100 21 0110100 53 1010100 85 1110100 117 0010101 22 0110101 54 1010101 86 1110101 118 0010110 23 0110110 55 1010110 87 1110110 119 001011...

Page 559: ...zero but is always read as a zero The SSE1 bit enables a trigger event to initiate queue execution for any single scan operation on queue 1 The QADC64E clears the SSE1 bit when the single scan is com...

Page 560: ...rigger falling edge continuous scan mode 10100 Periodic timer continuous scan mode time QCLK period x 27 10101 Periodic timer continuous scan mode time QCLK period x 28 10110 Periodic timer timer cont...

Page 561: ...e requested by a CCW in queue 2 which has the pause bit set 2 SSE2 Queue 2 Single Scan Enable Bit SSE2 enables a single scan of queue 2 to start after a trigger event occurs The SSE2 bit may be set to...

Page 562: ...11 and an EOQ programmed in CCW15 the second sequence starts at CCW16 with a pause after CCW17 and an EOQ programmed in CCW39 With BQ2 set to CCW10 and the continuous scan mode selected queue executio...

Page 563: ...Interval timer single scan mode time QCLK period x 216 01110 Interval timer single scan mode time QCLK period x 217 01111 Reserved mode 10000 Reserved mode 10001 Software triggered continuous scan mod...

Page 564: ...nverted and the result is stored in the result table The end of queue 1 is identified when execution is complete on the CCW in the location prior to that pointed to by BQ2 when the current CCW contain...

Page 565: ...an mode the pause flag will not set and execution continues without pausing This has allowed for the added definition of PF1 in the external gated modes PF1 is maintained by the QADC64E regardless of...

Page 566: ...all scan modes 4 TOR1 Queue 1 Trigger Overrun TOR1 indicates that an unexpected trigger event has occurred for queue 1 TOR1 can be set only while queue 1 is in the active state A trigger event genera...

Page 567: ...ble 14 17 shows the bits in the QS field and how they affect the status of queue 1 and queue 2 Refer to Section 14 5 Trigger and Queue Interaction Examples which shows the 4 bit queue status field tra...

Page 568: ...nterval Timer Trigger Single scan Pauses Yes Periodic Interval Timer Continuous scan Pauses Yes Software Initiated Single scan Continues Yes Software Initiated Continuous scan Continues Yes External G...

Page 569: ...er pending when a trigger event occurs for queue 2 while queue 1 is active In the opposite case when a trigger event occurs for queue 1 while queue 2 is active queue 2 is aborted and the status is rep...

Page 570: ...This field is a software read only field and write operations have no effect CWPQ1 allows software to read the last executed CCW in queue 1 regardless of which queue is active The CWPQ1 field is a CC...

Page 571: ...scan sequence the software writes to the CCW table to specify the desired channel conversions The software also establishes the criteria for initiating the queue execution by programming the queue ope...

Page 572: ...cycles When an analog to digital conversion is complete the result is written to the corresponding location in the result word table The QADC64E continues to sequentially execute each CCW in the queu...

Page 573: ...e module for a loss of clocks The QADC64E aborts any conversion in progress when the stop mode is entered When the freeze enable bit is set by software and the IMB3 internal FREEZE line is asserted th...

Page 574: ...is used by the application As far as the queue scanning operations are concerned there is no distinction between an internally or externally multiplexed analog input Refer to Section 14 2 5 External...

Page 575: ...nations Multiplexed Input Signals Channel Number in CCW CHAN Field Port Signal Name Analog Signal Name Other Functions Descriptions Signal Type Binary Decimal ANw B_PQB0 AN0 to AN7 Input 0000000 to 00...

Page 576: ...d table While there is only one result word table the data can be accessed in three different data formats Right justified in the 16 bit word with zeros in the higher order unused bits Left justified...

Page 577: ...d by an application software could use the corresponding locations in the result word table as scratch pad RAM remembering that only 10 bits are implemented The result alignment is only implemented fo...

Page 578: ...resolution time Initial sample time refers to the time during which the selected input channel is coupled through the buffer amplifier to the sample capacitor This buffer is used to quickly reproduce...

Page 579: ...endix F Electrical Characteristics for specific current levels 14 3 13 Sample Buffer Amplifier The sample buffer is used to raise the effective input impedance of the A D converter so that external co...

Page 580: ...tate Machine The state machine receives the QCLK RST STOP IST CHAN 6 0 and START CONV signals from which it generates all timing to perform an A D conversion The start conversion signal START CONV ind...

Page 581: ...queue 1 the current queue 2 conversion is aborted The status register reports the queue 2 status as suspended Any trigger events occurring for queue 2 while queue 2 is suspended are captured as trigge...

Page 582: ...ch sub queue refer to Figure 14 22 Refer to Section 14 4 4 Scan Modes for information on different scan modes The choice of single scan or continuous scan applies to the full queue and is not applied...

Page 583: ...7 Control Register 2 for more information on BQ2 The end of queue condition is recognized a conversion is performed the completion flag is set and the queue becomes idle BQ2 is set to CCW0 and a trigg...

Page 584: ...by a queue is performed In continuous scan mode multiple passes through a sequence of conversions defined by a queue are executed The possible modes are Disabled and reserved mode Single scan modes S...

Page 585: ...e queue The single scan enable bit remains set until the queue is completed After the queue reaches completion the QADC64E resets the single scan enable bit to zero If the single scan enable bit is wr...

Page 586: ...r edge The external trigger single scan mode is useful when the input trigger rate can exceed the queue execution rate Analog samples can be taken in sync with an external event even though the softwa...

Page 587: ...to be initiated by the periodic interval timer The periodic interval timer generates a trigger event whenever the time interval elapses The trigger event may cause the queue execution to continue fol...

Page 588: ...el 63 the last queue conversion to the first queue conversion requires 1 additional CCW fetch cycle Therefore continuous samples are not coherent at this boundary In addition the time from trigger to...

Page 589: ...ution to continue from the paused state Some applications need to synchronize the sampling of analog channels to external events There are cases when it is not possible to use software initiation of t...

Page 590: ...end of queue has been detected the next trigger event causes queue execution to begin again with the first CCW in the queue The periodic interval timer generates a trigger event whenever the time inte...

Page 591: ...fSYSCLK The software establishes the frequency of QCLK waveform by setting the PRESCALER field in the QACR0 register When the value of PRESCALER 0 the resulting frequency of QCLK is calculated using...

Page 592: ...periodic interval timer provided queue 1 is not in a mode which uses the periodic interval timer Roll over of the timer During the low power stop mode the periodic timer is held in reset Since low pow...

Page 593: ...om the IMB3 to the QADC64E require two clocks However if the CPU tries to access table locations while the QADC64E is accessing them the QADC64E produces IMB3 wait states From one to four IMB3 wait st...

Page 594: ...l 16 bits of data is written to and read from the QADC64E location with each access 16 bit accesses to an odd address require two bus cycles one byte of two different 16 bit QADC64E locations is acces...

Page 595: ...rigger events that are intended to initiate conversions and they can occur asynchronously in relation to each other and other conversions in progress For example a queue can be idle awaiting a trigger...

Page 596: ...not shown because they exist only very briefly between stable status conditions The first three examples in Figure 14 25 through Figure 14 27 S1 S2 and S3 show what happens when a new trigger event i...

Page 597: ...tion of the previous queue leaving software little time to retrieve the previous results Also when trigger events are occurring at a high rate for queue 1 the lower priority queue 2 channels may not g...

Page 598: ...Situation S5 Figure 14 29 shows that when multiple queue 2 trigger events are detected while queue 1 is busy the trigger overrun error bit is set but queue 1 execution is not disturbed Situation S5 a...

Page 599: ...complete so that queue 1 execution can begin Queue 2 is considered suspended After queue 1 is finished queue 2 starts over with the first CCW when the RES resume control bit is set to 0 Situation S7 F...

Page 600: ...es execution with the aborted CCW not the first CCW in the queue Figure 14 32 CCW Priority Situation 8 QADC S7 T1 T1 PAUSE Q1 Q2 QS IDLE IDLE IDLE 0010 0110 1010 0010 ACTIVE 0000 IDLE Q1 PF1 C1 C2 000...

Page 601: ...rmits the software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being lost Figure 14 34 CCW Priority Situation 10 QADC S9 T1 Q1 Q2 QS IDLE IDLE ACT IDLE 0010...

Page 602: ...rogress unlike queue 1 suspending queue 2 After the freeze condition is removed the QADC64E continues queue execution with the next CCW in sequence Trigger events that occur during freeze are not capt...

Page 603: ...e 14 38 CCW Freeze Situation 14 Figure 14 39 CCW Freeze Situation 15 Figure 14 40 CCW Freeze Situation 16 QADC S13 C1 C2 T2 Q2 CF2 C3 C4 FREEZE QADC S14 C1 C2 T1 Q1 CF1 C3 C4 FREEZE T1 T1 T2 T2 TRIGGE...

Page 604: ...g examples Example 1 below shows the timing for basic conversions where the following is assumed Q1 begins with CCW0 and ends with CCW3 CCW0 has pause bit set CCW1 does not have pause bit set External...

Page 605: ...e bit is set CCW0 please note that CWP does not increment until triggered When the pause is not set CCW1 the CWP increments with EOC The conversion results Q1 RES x show the result associated with CCW...

Page 606: ...reflect the condition that a gate closing occurred before the queue completed is a proposal under consideration at this time as example 2 NOTE At the end of Q1 the completion flag CF1 sets and the que...

Page 607: ...Port Digital Input Output Signals The sixteen port signals can be used as analog inputs or as a bidirectional 16 bit digital input output port Port A signals are referred to as PQA 7 0 when used as a...

Page 608: ...The QADC64E uses two external trigger signals ETRIG 2 1 Each of the two input external trigger signals is associated with one of the scan queues queue 1 or queue 2 The assignment of ETRIG 2 1 to a que...

Page 609: ...an VSSA the sample amplifier can never transfer a zero value Figure 14 48 shows the results of reference voltages outside the range defined by VDDA and VSSA At the top of the input signal range VDDA i...

Page 610: ...in mixed signal systems or in stand alone analog systems Close attention must be paid not to introduce additional sources of noise into the analog circuitry Common sources of noise include ground loop...

Page 611: ...all analog ground points in the circuit Bypass capacitors should be as close to the power signals as possible The analog ground should be isolated from the digital ground This can be done by cutting...

Page 612: ...Input Signals Analog inputs should have low AC impedance at the signals Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input signal of the part...

Page 613: ...tion characteristics etc All parasitic capacitance associated with the input signal is included in the value of the external capacitor Inductance is ignored The on resistance of the internal switches...

Page 614: ...MC54HC4052 MC74HC4052 MC54HC4053 etc RSOURCE 2 C FILTER CSOURCE R FILTER 2 CMUXIN RSOURCE 2 CFILTER CSOURCE RFILTER 2 CMUXIN RSOURCE 2 CFILTER CSOURCE RFILTER 2 CMUXIN RSOURCE 2 CFILTER CSOURCE RFILT...

Page 615: ...his filter into account 14 6 5 3 Error Resulting from Leakage A series resistor limits the current to a signal therefore input leakage acting through a large source impedance can degrade A D accuracy...

Page 616: ...results on neighboring inputs Parasitic devices associated with CMOS processes can cause an immediate disruptive influence on neighboring signals Common examples of parasitic devices are diodes to su...

Page 617: ...channel RSELECTED Source impedance on channel selected for conversion The current into IIN the neighboring signal is determined by the KN current coupling ratio of the parasitic bipolar transistor KN...

Page 618: ...QADC64E Enhanced Mode Operation MPC561 MPC563 Reference Manual Rev 1 2 14 76 Freescale Semiconductor...

Page 619: ...control information The duplicate independent SCIs are full duplex universal asynchronous receiver transmitter UART serial interface The original QSM SCI is enhanced by the addition of an SCI a common...

Page 620: ...ode fault flag Easily interfaces to simple expansion parts A D converters EEPROMS display drivers etc QSPI enhanced features are as follows Programmable Queue up to 32 preprogrammed transfers Programm...

Page 621: ...ble bits May be interrupt driven Four separate interrupt enable bits Two independent operating SCI modules Standard SCI receiver features Receiver wakeup function idle or address mark bit Idle line de...

Page 622: ...SCI1Control Register 0 SCC1R0 See XrefBlue Table 15 24 for bit descriptions S U 0x30 500A SCI1Control Register 1 SCC1R1 See XrefBlue Table 15 25 for bit descriptions S U 0x30 500C SCI1 Status Registe...

Page 623: ...es as well as the QSPI RAM All registers and RAM can be accessed on byte 8 bits half word 16 bits and word 32 bit boundaries Word accesses require two consecutive IMB3 bus cycles S U 0x30 5020 SCI2 Co...

Page 624: ...in QSMCMMCR determines how the QSMCM responds when the IMB3 FREEZE signal is asserted FREEZE is asserted when the CPU enters background debug mode Setting FRZ1 causes the QSPI to halt on the first tra...

Page 625: ...terrupt sources place their asserted level on a time multiplexed bus during four different time slots with eight levels communicated per slot The ILBS 0 1 signals indicate which group of eight are bei...

Page 626: ...for interfacing to the CPU and the intermodule bus This register can be modified only when the CPU is in supervisor mode MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field STOP FRZ1 SUPV SRESET 0 0 0...

Page 627: ...op enable Refer to Section 15 4 1 Low Power Stop Operation 0 Normal clock operation 1 Internal clocks stopped 1 FRZ1 Freeze1 bit Refer to Section 15 4 2 Freeze Operation 0 Ignore the FREEZE signal 1 H...

Page 628: ...it makes the corresponding pin an input setting a bit makes the pin an output DDRQS affects both QSPI function and I O function Table 15 8 summarizes the effect of DDRQS bits on QSPI pin function DDRQ...

Page 629: ...can be written either as a half word 16 bit or as 2 individual bytes 8 bit This allows the SCI GPIO pin data to written separately than the QSPI GPIO pin values This allows either the SCI pins or the...

Page 630: ...y PQSPAR as general purpose I O pins are controlled only by PQSDDR and PQSPDR the QSPI has no effect on these pins PQSPAR does not affect the operation of the SCI submodule Table 15 9 summarizes the Q...

Page 631: ...C S2 QPAPC S1 QPAPC S0 QPAMOSI QPAMISO DDRQS SRESET 0000_0000_0000_0000 Addr 0x30 5016 Note See bit descriptions in Table 15 11 Figure 15 8 PORTQS Pin Assignment Register PQSPAR Table 15 10 PQSPAR Bit...

Page 632: ...escriptions in Table 15 10 Figure 15 9 PORTQS Data Direction Register DDRQS Table 15 11 DDRQS Bit Descriptions Bits Name Description 0 7 PQSPAR PORTSQS pin assignment register See Section 15 5 2 PORTQ...

Page 633: ...MHz IMB3 clock can be programmed The default delay is 17 clocks 0 425 s at 40 MHz Programmable delay simplifies the interface to devices that require different delays between transfers QSPI Block Cont...

Page 634: ...onverters by continuously updating conversion values stored in the RAM Continuous transfer mode allows transfer of an uninterrupted bit stream From 8 to 512 bits can be transferred without CPU interve...

Page 635: ...nt serial transfer is completed the new SPCR2 value becomes effective 15 6 1 1 QSPI Control Register 0 SPCR0 SPCR0 contains parameters for configuring the QSPI before it is enabled The CPU has read wr...

Page 636: ...a transfers from 8 to 16 bits are supported Illegal reserved values default to eight bits Table 15 14 shows the number of bits per transfer 6 CPOL Clock polarity CPOL is used to determine the inactive...

Page 637: ...g Disabling and Halting the SPI 0 QSPI is disabled QSPI pins can be used for general purpose I O 1 QSPI is enabled Pins allocated by PQSPAR are controlled by the QSPI 1 7 DSCKL Delay before SCK When t...

Page 638: ...0_0000_0000_0000 Addr 0x30 501C Figure 15 13 SPCR2 QSPI Control Register 2 Table 15 16 SPCR2 Bit Descriptions Bits Name Description 0 SPIFIE SPI finished interrupt enable Refer to Section 15 6 4 2 QSP...

Page 639: ...trols feedback on the data serializer for testing 0 Feedback path disabled 1 Feedback path enabled 6 HMIE HALTA and MODF interrupt enable HMIE enables interrupt requests generated by the HALTA status...

Page 640: ...SPIF is set after execution of the command at the address in ENDQP in SPCR2 If wraparound mode is enabled WREN 1 the SPIF is set after completion of the command defined by ENDQP each time the QSPI cy...

Page 641: ...lely to input data then this segment does not need to be initialized Data must be written to transmit RAM in a right justified format The QSPI cannot modify information in the transmit RAM The QSPI co...

Page 642: ...RAM Bit Descriptions Bits Name Description 0 CONT Continue 0 Control of chip selects returned to PORTQS after transfer is complete 1 Peripheral chip selects remain asserted after transfer is complete...

Page 643: ...nts to the command currently being executed The completed queue pointer CPTQP contained in SPSR points to the last command executed The end queue pointer ENDQP contained in SPCR2 points to the final c...

Page 644: ...n error condition called mode fault MODF also clears SPE This error occurs when PCS0 SS is configured for input the QSPI is a system master MSTR 1 and PCS0 SS is driven low externally Setting the HALT...

Page 645: ...a queue of commands defined by control bits in each command RAM queue entry Chip select pins are activated data is transmitted from the transmit RAM and received by the receive RAM In slave mode oper...

Page 646: ...28 Freescale Semiconductor Figure 15 18 Flowchart of QSPI Initialization Operation Initialize QSMCM Global Registers Initialize QSPI Control Registers Initialize PQSPAR PORTQS and DDRQS Initialize QS...

Page 647: ...rol and Transmit Data From RAM Using Queue Pointer Address A1 Working Queue Pointer Changed to NEWQP Is QSPI Disabled N Y N Execute Serial Transfer Store Received Data In RAM Using Queue Pointer Addre...

Page 648: ...5 30 Freescale Semiconductor Figure 15 20 Flowchart of QSPI Master Operation Part 2 Is Delay After Transfer Asserted Y N Execute Programmed Delay B1 Write Queue Pointer To CPTQP Status Bits C1 Negate...

Page 649: ...us Flag Request Interrupt Is Interrupt Enable Bit SPIFIE Set Is Wrap Enable Bit Set Y N Reset Working Queue Pointer to NEWQP or 0x0000 Y Disable QSPI A1 N Increment Working Queue Pointer N Is HALT Or...

Page 650: ...n Part 1 Read Transmit Data From RAM Using Queue Pointer Address A2 Queue Pointer Changed to NEWQP N Y N Write Queue Pointer to CPTQP Status Bits Store Received Data In RAM Using Queue Pointer Address...

Page 651: ...st Interrupt Is Interrupt Enable Bit SPIFIE Set Is Wrap Enable Bit Asserted Y N Reset Working Queue Pointer To NEWQP or 0x0000 Y Disable QSPI A2 N Increment Working Queue Pointer N Is HALT or FREEZE A...

Page 652: ...y depending on the particular application SCK is the serial clock output in master mode and must be assigned to the QSPI for proper operation The PORTQS data register must next be written with values...

Page 653: ...he SPIFIE bit in SPCR2 is set an interrupt request is generated when SPIF is asserted At this point the QSPI clears SPE and stops unless wraparound mode is enabled 15 6 5 1 Clock Phase and Polarity In...

Page 654: ...alf the SCK period 15 6 5 4 Delay After Transfer Delay after transfer can be used to provide a peripheral deselect interval A delay can also be inserted between consecutive transfers to allow serial A...

Page 655: ...ignal can be asserted at a time and more than one external device can be connected to the PCS pins provided proper fanout is observed PCS0 shares a pin with the slave select SS signal which initiates...

Page 656: ...e end of the queue is reached the SPIF flag is set SPIF is not automatically reset If interrupt driven QSPI service is used the service routine must clear the SPIF bit to end the current interrupt req...

Page 657: ...zer from the pointer address in transmit RAM and transmitted Transfer is synchronized with the externally generated SCK The CPHA and CPOL bits determine upon which SCK edge to latch incoming data from...

Page 658: ...ects as outputs PCS0 SS is used as an input Although CONT cannot be used in slave mode a provision is made to enable receipt of more than 16 data bits While keeping the QSPI selected PCS0 SS is held l...

Page 659: ...ch incoming SCK edge the MOSI pin uses to latch incoming data and which edge the MISO pin uses to drive the data out The QSPI transmits and receives data until reaching the end of the queue defined as...

Page 660: ...hat another MCU is requesting to become the SPI network master or simply that the hardware is incorrectly affecting PCS0 SS SPE in SPCR1 is cleared disabling the QSPI The QSPI pins revert to control b...

Page 661: ...Control H 8 7 6 5 4 3 2 1 0 L 10 11 Bit TX Shift Register TxD SCxDR TX Buffer TRANSFER Tx Buffer SHIFT Enable JAM Enable PREAMBLE JAM 1 s BREAK JAM 0 s Force Pin Direction Out SIZE 8 9 Parity Generat...

Page 662: ...WAKE RIE ILIE TE RE RWU SBK TIE TCIE SCCxR1 CONTROL Register 1 0 15 FE NF OR IDLE RDRF TC TDRE SCxSR STATUS Register PF RAF 15 0 Wake up Logic Pin Buffer RxD MSB All Ones Data Recovery 16 Parity Detec...

Page 663: ...able 15 23 SCI Registers Address Name Usage 0x30 5008 SCC1R0 SCI1 Control Register 0 See XrefBlue Table 15 24 for bit descriptions 0x30 500A SCC1R1 SCI1 Control Register 1 See XrefBlue Table 15 25 for...

Page 664: ...ister values allow the SCI to complete the current transfer then disable the receiver and transmitter 0x30 502C 0x30 504A QSCI1 Transmit Queue Memory Area QSCI1 Transmit Queue Data locations on half w...

Page 665: ...e 0 Normal SCI operation no looping feedback path disabled 1 SCI test operation looping feedback path enabled 2 WOMS Wired OR mode for SCI Pins 0 If configured as an output TXD is a normal CMOS output...

Page 666: ...written the SCxDR the newly set status bit is not cleared Instead SCxSR must be read again with the bit set and SCxDR must be read or written before the status bit is cleared NOTE None of the status...

Page 667: ...ifter are transferred to register RDRx If one or more errors are detected in the received word the appropriate flag s NF FE or PF are set within the same clock cycle 0 Receive data register is empty o...

Page 668: ...op bit s It is not set by noise on the idle line or on invalid start bits Each bit is sampled three times for noise If the three samples are not at the same logic level the majority value is used for...

Page 669: ...least three receive time samples of logic one Stop bit One bit time of logic one that indicates the end of a data frame MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field R8 T8 R7 T7 R6 T6 R5 T5 R4...

Page 670: ...erial interfaces is one start bit eight data bits Lsb first and one stop bit ten bits total The most common 11 bit data frame contains one start bit eight data bits a parity or control bit and one sto...

Page 671: ...set the MSB of data in a frame i e the bit preceding the stop bit is used for the parity function For transmitted data a parity bit is generated For received data the parity bit is checked When parit...

Page 672: ...w data is transferred from TDRx to the transmit serial shifter and TDRE is set automatically An interrupt may optionally be generated at this point The transmission complete TC flag in SCxSR shows tra...

Page 673: ...an be separated with minimum idle time by using a preamble of 10 bit times 11 if a 9 bit data format is specified of marks logic ones Follow these steps 1 Write the last data frame of the first messag...

Page 674: ...noise flag Go to step 3 and clear RAF Otherwise place RT5 in the pipeline and proceed to step 8 8 Skip RT6 and sample RT7 If any two of RT3 RT5 or RT7 is high RT1 was noise only set an internal worki...

Page 675: ...ng data stream From this point on data movement is synchronized with the MCU IMB3 clock Operation of the receiver state machine is detailed in the Queued Serial Module Reference Manual The number of b...

Page 676: ...e M bit in SCCxR1 The SCI receiver has both short and long idle line detection capability Idle line detection is always enabled The idle line type ILT bit in SCCxR1 determines which type of detection...

Page 677: ...s frame When the MSB of a frame is set the receiver clears RWU and wakes up The data frame is received normally transferred to the RDRx and the RDRF flag is set If software does not recognize the addr...

Page 678: ...F flag in QSCI1SR is set The interrupt is blocked by negating QBHFI This bit refers to the queue locations SCRQ 8 15 0 QBHF interrupt inhibited 1 Queue bottom half full QBHF interrupt enabled 6 QTHEI...

Page 679: ...15 32 QSCI1 Status Register QSCI1SR Table 15 33 QSCI1SR Bit Descriptions Bits Name Description 0 2 Reserved 3 QOR Receiver queue overrun error The QOR is set when a new data frame is ready to be trans...

Page 680: ...TQ 0 7 still contain data to be sent to the transmit serial shifter 1 New data may now be written to the queue locations SCTQ 0 7 7 QBHE Transmitter queue bottom half empty QBHE is set when all the da...

Page 681: ...C function as previously defined Locations SCTQ 0 15 can be used as general purpose 9 bit registers All other bits pertaining to the queue should be ignored by software Programmable queue up to 16 tra...

Page 682: ...owed by a write of QBHE to zero In order to implement the transmit queue QTE must be set QSCI1CR TE must be set SCC1R1 QTHE must be cleared QSCI1SR and TDRE must be set SC1SR Enable and disable option...

Page 683: ...Hardware Software Load QPEND with QTSZ Increment QTPNT QTPNT 1000 QBHE 0 Reset QTPNT to 0000 Write QTSZ n Clear QTHE TC Write SCTQ 0 n Set TE QTE 1 TE 1 No Yes TDRE 1 QTHE 0 Refers to Action Performed...

Page 684: ...e Set QTE and TE 1 Enable Queue Interrupt for First Use of the Queue If Finished Transmitting Then Clear QTE and or TE If Finished Transmitting Then Clear QTE and or TE DONE DONE Read Status Register...

Page 685: ...re 15 36 Queue Transmit Example for 17 Data Bytes 0000 0111 1000 1111 QTPNT QPEND 1111 1000 0111 0000 QTSZ 1111 16 Data Frames SCTQ0 SCTQ7 SCTQ8 SCTQ15 Write New QTSZ for When Wrap Occurs QTSZ 0 16 1...

Page 686: ...rial Multi Channel Module MPC561 MPC563 Reference Manual Rev 1 2 15 68 Freescale Semiconductor 15 8 7 Example SCI Transmit for 25 Data Bytes Figure 15 37 below is an example of a transmission of 25 da...

Page 687: ...8 SCTQ15 0000 0111 1000 1111 QTPNT QPEND 1111 1000 0111 0000 QTSZ 1111 16 Data Frames SCTQ0 SCTQ7 SCTQ8 SCTQ15 0001 0000 0111 1000 1111 QTPNT QPEND 1000 QTSZ 1000 9 Data Frames SCTQ0 SCTQ7 SCTQ8 SCTQ1...

Page 688: ...l SCI1 implemented by the queue receiver enable QRE bit set by software When the queue is enabled software should ignore the RDRF bit When the queue is disabled QRE 0 the SCI functions in single buffe...

Page 689: ...THF and QBHF as controlled by the QTHFI and QBHFI respectfully 4 bit counter QRPNT is used as a pointer to indicate where the next valid data frame will be stored A queue overrun error flag QOR to ind...

Page 690: ...PC563 Reference Manual Rev 1 2 15 72 Freescale Semiconductor but the data register SC1DR is still full The data in the shifter that generated the OR assertion is overwritten by the next received data...

Page 691: ...RE Load RX Data to QRPNT 0000 No Yes SCRQ QRPNT QRE 0 QOR 0 Hardware Software Refers to Action Performed In Parallel QTHF 1 QBHF 1 QTHFI 0 QBHFI 0 No Yes Set QTHFI QBHFI Clear QTHF QBHF Set RE Reset I...

Page 692: ...Reset Configure the Receive Queue QBHF 1 Yes No Read Status Register With QBHF 1 Read SCRQ 8 15 Read Status Register With QTHFI QBHFI 1 Set QRE and RE 1 QTHF 1 Read SCRQ 0 7 Read Status Register with...

Page 693: ...p of the figure and going left to right and then down the page Figure 15 41 Queue Receive Example for 17 Data Bytes 0000 0111 1000 1111 QRPNT SCRQ0 SCRQ7 SCRQ8 SCRQ15 0000 0111 1000 1111 QRPNT SCRQ0 S...

Page 694: ...Queued Serial Multi Channel Module MPC561 MPC563 Reference Manual Rev 1 2 15 76 Freescale Semiconductor...

Page 695: ...2 0 part B The third TouCAN has its signals muxed with MIOS14 GPIO or QSMCM SCI2 signals These signals are configured as GPIO inputs at reset and must be changed to TouCAN signals in the MIOS before e...

Page 696: ...ber Time stamp based on 16 bit free running timer Global network time synchronized by a specific message Programmable I O modes Maskable interrupts Independent of the transmission medium external tran...

Page 697: ...TX0 and CNRX0 signals of TouCAN_C are shared with MIOS14 GPIO signals MPIO32B11 MPIO32B12 or QSMCM SCI2 signals TXD2 QGPO2 RXD2 QGPI2 The signal functions for these signals are controlled by the PDMCR...

Page 698: ...ID 14 0 RTR ID_LOW 0x6 Data Byte 0 Data Byte 1 0x8 Data Byte 2 Data Byte 3 0xA Data Byte 4 Data Byte 5 0xC Data Byte 6 Data Byte 7 0xE Reserved Figure 16 3 Extended ID Message Buffer Structure MSB 0 7...

Page 699: ...buffer is active and empty 0b0010 0b0010 FULL message buffer is full 0b0110 If a CPU read occurs before the new frame new receive code is 0010 0b0110 OVERRUN addtional frame was received into a full...

Page 700: ...f extended format frame is used this field should be set to one If zero standard format frame should be used ID 14 0 Bits 14 0 of the extended identifier located in the ID_LOW word of the message buff...

Page 701: ...buffer triggers the lock for that buffer While locked a received message cannot be transferred into that buffer from one of the serial message buffers If a message transfer between the message buffer...

Page 702: ...gainst the incoming ID bit to see if a match exists Table 16 7 Mask Examples for Normal Extended Messages Message Buffer MB Mask Base ID ID 28 18 IDE Extended ID ID 17 0 Match MB2 1 1 1 1 1 1 1 1 0 0...

Page 703: ...mple point indicated in Figure 16 5 is the position of the actual sample point if a single sample per bit is selected CANCTRL1 SAMP bit 0 If three samples per bit are selected the sample point indicat...

Page 704: ...ssion and arbitrate against the message which transmitted the early SOF The TouCAN bit time must be programmed to be greater than or equal to nine system clocks or correct operation is not guaranteed...

Page 705: ...gister is updated to reflect a bus off state and an interrupt may be issued The value of the Tx error counter is reset to zero If the TouCAN is in the bus off state the Tx error counter and an additio...

Page 706: ...tionally be reset upon the reception of a frame into message buffer 0 This feature allows network time synchronization to be performed 16 4 TouCAN Operation The basic operation of the TouCAN can be di...

Page 707: ...tion mode LBUF bit in CANCTRL1 2 Initialize message buffers a The control status word of all message buffers must be written either as an active or inactive message buffer b All other entries in each...

Page 708: ...ion the value of the free running timer which was captured at the beginning of the identifier field on the CAN bus is written into the time stamp field in the message buffer The code field in the cont...

Page 709: ...s is written into the time stamp field in the message buffer 3 The ID field data field and Rx length field are stored 4 The code field is updated 5 The status flag is set in the IFLAG register The use...

Page 710: ...ssage buffer by reading its control status word or globally releases any locked message buffer by reading the free running timer 3 If a receive frame with a matching ID is received during the time the...

Page 711: ...e buffer It is only used to trigger the automatic transmission of a frame in response The mask registers are not used in remote frame ID matching All ID bits except RTR of the incoming received frame...

Page 712: ...waits for the completion of all internal activity except in the CAN bus interface to be complete Then the following events occur The TouCAN shuts down its clocks stopping most internal circuits thus a...

Page 713: ...ug mode when the STOP bit is set the TouCAN assumes that debug mode should be exited As a result it tries to synchronize with the CAN bus and only then does it await the conditions required for entry...

Page 714: ...ted in the error and status register ESTAT The bus off and error interrupt mask bits BOFFMSK and ERRMSK are located in CANCTRL0 and the wake up interrupt mask bit WAKEMSK is located in the module conf...

Page 715: ...the lower 128 bytes some are not used Registers with bits marked as reserved should always be written as logic 0 Typically the TouCAN control registers are programmed during system initialization bef...

Page 716: ...bit descriptions S U 0x30 7094 A 0x30 7494 B 0x30 7894 C Receive Buffer 14 Mask High RX14MSKHI_x See Section 16 7 10 Receive Buffer 14 Mask Registers RX14MSKHI RX14MSKLO for bit descriptions S U 0x30...

Page 717: ...or message buffer definitions S U 0x30 7160 0x30 716F A 0x30 7560 0x30 756F B 0x30 7960 0x30 796F C MBUFF6 1 TouCAN X Message Buffer 6 See Figure 16 3 and Figure 16 4 for message buffer definitions S...

Page 718: ...gure 16 3 and Figure 16 4 for message buffer definitions 1 The last word of each of the MBUFF arrays address 0x E is reserved and may cause an RCPU exception if read Table 16 10 TouCAN Register Map co...

Page 719: ...ion 16 5 1 Debug Mode for more information 0 TouCAN ignores the IMB3 FREEZE signal and the HALT bit in the module configuration register 1 TouCAN module enabled to enter debug mode 2 Reserved 3 HALT H...

Page 720: ...9 SELFWAKE Self wake enable This bit allows the TouCAN to wake up when bus activity is detected after the STOP bit is set If this bit is set when the TouCAN enters low power stop mode the TouCAN will...

Page 721: ...Table 16 12 CANICR Bit Descriptions Bits Name Description 0 4 Reserved 5 7 IRL Interrupt request level When the TouCAN generates an interrupt request this field determines which of the interrupt requ...

Page 722: ...n CNRX0 X 0 0 CNRX0 signal is interpreted as a dominant bit 1 CNRX0 signal is interpreted as a recessive bit X 1 0 CNRX0 signal is interpreted as a recessive bit 1 CNRX0 signal is interpreted as a dom...

Page 723: ...eature provides the means to synchronize multiple TouCAN stations with a special SYNC message global network time 0 Timer synchronization disabled 1 Timer synchronization enabled Note there can be a b...

Page 724: ...ANCTRL2 Table 16 18 CANCTRL2 Bit Descriptions Bits Name Description 0 7 PRESDIV See Table 16 17 8 9 RJW Resynchronization jump width The RJW field defines the maximum number of time quanta a bit time...

Page 725: ...or transmitted When there is no message on the bus it increments at the nominal bit rate The timer value is captured at the beginning of the identifier field of any frame on the CAN bus The captured v...

Page 726: ...te to this bit MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field MID2 8 MID2 7 MID2 6 MID2 5 MID2 4 MID2 3 MID2 2 MID2 1 MID2 0 MID1 9 MID1 8 0 1 MID 17 MID 16 MID 15 SRESET 1 1 1 1 1 1 1 1 1 1 1 0 1 1...

Page 727: ...ID 4 MID 3 MID 2 MID 1 MID 0 0 SRESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Figure 16 18 Receive Buffer 15 Mask Registers High RX15MSKHI Low RX15MSKLO Table 16 22 RX15MSKHI RX15MSKLO Field Descriptions Bits...

Page 728: ...5 STUFFERR Bit stuff error The STUFFERR bit indicates whether or not the bit stuffing that occurred in the last transmitted or received message was correct 0 No bit stuffing error was detected since t...

Page 729: ...t first read it as a one then write as a zero Writing a one has no effect 15 WAKEINT Wake interrupt The WAKEINT bit indicates that bus activity has been detected while the TouCAN module is in low powe...

Page 730: ...Name Description 0 7 8 15 IFLAGH IFLAGL IFLAG contains two 8 bit fields IFLAGH and IFLAGL IFLAG can be accessed with a 16 bit read or write and IFLAGH and IFLAGL can be accessed with byte reads or wri...

Page 731: ...CAN 2 0B Controller Module MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor 16 37...

Page 732: ...CAN 2 0B Controller Module MPC561 MPC563 Reference Manual Rev 1 2 16 38 Freescale Semiconductor...

Page 733: ...is composed of submodules it is easily configurable for different kinds of applications The MIOS14 is composed of the following submodules One MIOS14 bus interface submodule MBISM One MIOS14 counter p...

Page 734: ...M13 MDASM14 MDASM15 MDASM 27 MDASM28 MDASM29 MDASM30 MDASM31 MDA12 MDA31 CB23 PWM18 CB8 CB22 CB6 CB7 MCPSM MPWM21 PWM PWMSM21 MPWM16 PWM MPWMSM16 MPWM5 PWM PWMSM5 MPWM0 PWM PWMSM0 Channel and I O Sign...

Page 735: ...ternal signal fSYS 4 Flag setting and possible interrupt generation on overflow of the up counter Time counter on internal clock with interrupt capability after a pre determined time Optional signal u...

Page 736: ...tion 305 Hz 3 27 ms Minimum output frequency at fSYS 40 MHz with 16 bits of resolution and divide by 4096 prescaler selection 0 15 Hz 6 7 s Maximum output frequency at fSYS 40 MHz with eight bits of r...

Page 737: ...d by eight Refer to Table 17 1 This does not apply to the MBISM the MCPSM and the MIRSMs For these submodules refer to the MIOS14 memory map in Figure 17 2 17 2 2 Signal Naming Convention In Figure 17...

Page 738: ...same signal names for the inputs and outputs which are connected as shown in Table 17 1 17 3 MIOS14 Configuration The complete MIOS14 submodule and signal configuration is shown in Table 17 1 Table 1...

Page 739: ...080 PWM I O MPWM 16 MPWM 16 PWMSM 17 1 1 0x30 6088 PWM I O MPWM 17 MPWM 17 MDO3 PWMSM 18 1 2 0x30 6090 PWM I O MPWM 18 MPWM 18 MDO6 PWMSM 19 1 3 0x30 6098 PWM I O MPWM 19 MPWM 19 MDO7 PWMSM 20 1 4 0x3...

Page 740: ...GPIO MPIO32 B0 MPIO32 B0 VF0 MDO1 GPIO MPIO32 B1 MPIO32 B1 VF1 MCKO GPIO MPIO32 B2 MPIO32 B2 VF2 MSEI GPIO MPIO32 B3 MPIO32 B3 VFLS0 MSEO GPIO MPIO32 B4 MPIO32 B4 VFLS1 GPIO MPIO32 B5 MPIO32 B5 MDO5...

Page 741: ...4 is called the modular I O bus MIOB The MIOB makes communications possible between any submodule and the IMB3 bus master through the MBISM The MIOB is divided into three dedicated buses GPIO MPIO32 B...

Page 742: ...ubmodules Typically counter submodules drive the CBS while action submodules process the data on these buses Note however that some submodules are self contained and therefore independent of the count...

Page 743: ...Modular Input Output Subsystem MIOS14 MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor 17 11 17 4 2 Wait States The MIOS14 does not generate wait states...

Page 744: ...6C44 0x30 6C46 0x30 6C70 Reserved MIOS14LVL1 Reserved MIOS14RPR1 MIOS14ER1 MIOS14SR1 Reserved 0x30 6C42 MPWMSM0 MPWMSM1 MPWMSM2 MPWMSM3 0x30 6000 0x30 6008 0x30 6010 0x30 6018 MPWMSM4 MMCSM6 MDASM11...

Page 745: ...MBISM submodule 17 6 1 1 MIOS14 Test and Signal Control Register MIOS14TPCR This register is used for MIOS14 factory testing and to control the VF and VFLS Signal usage Control of other multiplexed f...

Page 746: ...always be programmed to a 0 1 13 Reserved 14 VF VF Pin Multiplex This bit controls the function of the VF pins VF0 MPIO32B0 VF1 MPIO32B1 VF2 MPIO32B2 0 MIOS14 General Purpose I O is selected MPIO32B0...

Page 747: ...et or until the STOP bit is written to zero by the CPU via the IMB3 The STOP bit is cleared by reset 0 Allows MIOS14 operation 1 Selectively stops MIOS14 operation 1 Reserved 2 FRZ Freeze enable The F...

Page 748: ...t of the MCPSM counter clock A block diagram of the MCPSM is given in Figure 17 8 The following sections describe the MCPSM in detail Figure 17 8 MCPSM Block Diagram 17 7 1 MCPSM Features Centralized...

Page 749: ...t possible situations The MIOS14 counter prescaler submodule does not use any 16 bit counter bus The MIOS14 counter prescaler submodule does not use the request bus 17 7 2 Effect of RESET on MCPSM Whe...

Page 750: ...l bit when set make possible a freeze of the MCPSM counter if the MIOB freeze line is activated NOTE This line is active when MIOS14MCR STOP is set or when MIOS14MCR FREN and the IMB3 FREEZE line are...

Page 751: ...bit up counter register a 16 bit modulus latch register counter loading and interrupt flag generation logic The contents of the modulus latch register is transferred to the counter under the following...

Page 752: ...internal MCPSM output fSYS 2 clocked by the external signal fSYS 4 Flag setting and possible interrupt generation on overflow of the up counter register 16 bit Up Counter Reg Edge 16 bit Counter Bus...

Page 753: ...rising or falling edge may be used according to the setting of these bits When the external clock source is selected the MMCSM is in the event counter mode The counter can simply counts the number of...

Page 754: ...ege level to access to the MMCSM registers depends on the MIOS14MCR SUPV bit The privilege level is unrestricted after SRESET and can be changed to supervisor by software 17 8 5 1 MMCSM Register Organ...

Page 755: ...Register MMCSMSCR MMCSM24 0x30 60C0 MMCSM24 Up Counter Register MMCSMCNT 0x30 60C2 MMCSM24 Modulus Latch Register MMCSMML 0x30 60C4 MMCSM24 Status Control Register Duplicated MMCSMSCRD 0x30 60C6 MMCS...

Page 756: ...ead only signal status bits read write control bits and an 8 bit read write data register as detailed below MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field ML SRESET Undefined Addr 0x30 6032 0x30...

Page 757: ...of the MMCSMCNT See Table 17 13 for details about edge sensitivity 5 6 CLS Clock select These read write control bits select the clock source for the modulus counter Either the rising edge or falling...

Page 758: ...erform two event operations such as PWM generation and measurement input capture output compare etc The MDASM is composed of two timing channels A and B an output flip flop an input edge detector and...

Page 759: ...t functions Software selection of one of the four possible 16 bit counter buses used for timing operations Flag setting and possible interrupt generation after MDASM action completion Software selecti...

Page 760: ...one 16 bit data register and one 16 bit comparator Channel B also consists of one 16 bit data register and one 16 bit comparator however internally channel B has two data registers B1 and B2 and the...

Page 761: ...es without passing via the disable mode does not guarantee the subsequent functionality 17 9 3 1 Disable DIS Mode The disable mode is selected by setting MODE 0 3 to 0b0000 In this mode all input capt...

Page 762: ...ure function remains disabled until the first leading edge triggers the first input capture on channel B refer to Figure 17 16 When this leading edge is detected the count value of the 16 bit counter...

Page 763: ...meaningless On the second and subsequent captures the FLAG line is activated when the data in register A is transferred to register B1 When the second edge of the same polarity is detected the counte...

Page 764: ...o the input period measurement mode IPM described above with the exception that the FLAG line is also activated at the occurrence of the first detected edge of the selected polarity In this mode the M...

Page 765: ...en though the contents of B1 are not used in this mode Both channels work together to generate one single shot output pulse signal Channel A defines the leading edge of the output pulse while channel...

Page 766: ...t circuit configurations can be selected using the WOR bit in the MDASMSCR register NOTE If both channels are loaded with the same value the output flip flop provides a logic zero level output and the...

Page 767: ...e the OCAB mode should be used to generate a flag on both the A and the B match NOTE In this mode registers A and B2 are accessible to the user software at consecutive addresses Figure 17 20 provides...

Page 768: ...B1 Register B2 is not accessible Channels A and B define respectively the leading and trailing edges of the PWM output pulse The value in register B1 is transferred to register B2 each time a match oc...

Page 769: ...egisters A and B must be loaded with the values needed to produce the desired PWM output pulse NOTE 16 bit counter bus compare only occurs when the 16 bit counter bus is updated Figure 17 21 provides...

Page 770: ...have a duty cycle ranging from 0 to 100 Setting bit 15 of the value stored in register B to one results in the output being always set Clearing bit 15 to zero allows normal comparisons to occur and t...

Page 771: ...el to access the MDASM registers depends on the MIOS14MCR SUPV The privilege level is unrestricted after reset and can be changed to supervisor by software 17 9 6 1 MDASM Registers Organization The MD...

Page 772: ...plicated MDASMSCRD 0x30 606E MDASM13 Status Control Register MDASMSCR MDASM14 0x30 6070 MDASM14 Data A Register MDASMAR 0x30 6072 MDASM14 Data B Register MDASMBR 0x30 6074 MDASM14 Status Control Regis...

Page 773: ...0 60F0 MDASM30 Data A Register MDASMAR 0x30 60F2 MDASM30 Data B Register MDASMBR 0x30 60F4 MDASM30 Status Control Register Duplicated MDASMSCRD 0x30 60F6 MDASM30 Status Control Register MDASMSCR MDASM...

Page 774: ...ising or falling edge OCB and OCAB modes MDASMAR is loaded with the value corresponding to the leading edge of the pulse to be generated Writing to MDASMAR in the OCB and OCAB modes also enables the c...

Page 775: ...er reads B1 or B2 depending on the mode selected In the DIS mode MDASMBR can be accessed to prepare a value for a subsequent mode selection In this mode register B1 is accessed in order to prepare a v...

Page 776: ...e last value written In the IPWM mode this bit is used to select the capture edge sensitivity of channels A and B 1 Channel A captures on a falling edge Channel B captures on a rising edge 0 Channel A...

Page 777: ...inputs are grounded 11 Reserved 12 15 MODE Mode select bits The four mode select bits select the mode of operation of the MDASM To avoid spurious interrupts it is recommended that MDASM interrupts ar...

Page 778: ...a double buffered mode to avoid spurious update The following sections describe the MPWMSM in detail A block diagram of the MPWMSM is shown in Figure 17 25 1110 9 0 6 OPWM Output pulse width modulatio...

Page 779: ...preset with a value between 128 and 255 it is said to have seven bits of resolution If it is preset with a value between 256 and 511 it is said to have eight bits of resolution and so on Resolution T...

Page 780: ...0 to 100 Possible interrupt generation at start of every period Software selectable output pulse polarity Software readable output signal status Possible use of signal as I O port when PWM function i...

Page 781: ...to the counter i e at the MPWMCNTR address it also writes to the MPWMPERR register When in transparent mode TRSP 1 writing to the MPWMPERR will also write to the counter The down counter is readable...

Page 782: ...by the following equation 17 10 3 4 Pulse Width Registers The pulse width section is composed of two 16 bit data registers MPWMPULR1 and MPWMPULR2 Only MPWMPULR1 is accessible by software The software...

Page 783: ...is being used to generate an analog level the 0 and 100 represent the full scale values The 0 output is created with a 0x0000 in register MPWMPULR2 which prevents the output flip flop from ever being...

Page 784: ...52K 104K 208K 416 K 833K 1666 K 3333K 175 ns 7 87 2 174 348 697 1395 2790 5580 11 1 K 22 3 K 44 6K 89 3 K 178K 357K 714K 1428 K 2857K 200 ns 8 76 3 152 305 610 1220 2441 4882 9765 19 5 K 39K 78K 156 K...

Page 785: ...9 15 24 30 51 61 03 122 244 1 488 2 976 5 1953 3906 7812 15 6K 38 4 s 1536 0 397 0 795 1 589 3 179 6 358 12 71 25 43 50 86 101 7 203 5 406 9 813 8 1627 3255 6510 13K 44 8 s 1792 0 34 0 681 1 362 2 724...

Page 786: ...operations 16 bit accesses are sufficient and long word accesses 32 bit are treated as two 16 bit accesses with one exception a long word write to the period pulse width registers In this case if the...

Page 787: ...es in this section are specified as offsets from the base address of the MPWMSM Table 17 25 MPWMSM Address Map Address Register MPWMSM0 0x30 6000 MPWMSM0 Period Register MPWMPERR See Table 17 26 for b...

Page 788: ...MPWMSM16 0x30 6080 MPWMSM16 Period Register MPWMPERR 0x30 6082 MPWMSM16 Pulse Register MPWMPULR 0x30 6084 MPWMSM16 Count Register MPWMCNTR 0x30 6086 MPWMSM16 Status Control Register MPWMSCR MPWMSM17...

Page 789: ...PWMSM20 Count Register MPWMCNTR 0x30 60A6 MPWMSM20 Status Control Register MPWMSCR MPWMSM21 0x30 60A8 MPWMSM21 Period Register MPWMPERR 0x30 60AA MPWMSM21 Pulse Register MPWMPULR 0x30 60AC MPWMSM21 Co...

Page 790: ...30 6082 0x30 608A 0x30 6092 0x30 609A 0x30 60A2 0x30 60AA Figure 17 27 MPWMSM Pulse Width Register MPWMPULR Table 17 27 MPWMPULR Bit Descriptions Bits Name Description 0 15 PUL Pulse width These bits...

Page 791: ...le buffered mode 1 Transparent mode The TRSP bit is cleared by reset 4 POL Output polarity control bit The POL bit works in conjunction with the EN bit and controls whether the MPWMSM drives the signa...

Page 792: ...I O capability for up to 16 signals The following sections describe the MPIOSM in detail A block diagram of one bit of the MPIOSM is shown in Figure 17 30 The MPIOSM contains 16 such blocks Figure 17...

Page 793: ...rmined by the state of the corresponding bit in the DDR The data direction register can be written to or read by the processor During the programmed output state a read of the data register reads the...

Page 794: ...n implemented in this submodule To be flexible while selecting the number of implemented signals the test patterns are implemented in a bit per bit modular fashion 17 11 7 MPIOSM Registers The privile...

Page 795: ...re treated in two different sections The interrupt request submodules MIRSM The interrupt control section ICS of the MBISM The MIRSM gathers in service request flags from each group of up to 16 submod...

Page 796: ...s Each MIRSM includes One 16 bit status register for the flags One 16 bit enable register for each implemented level One 16 bit IRQ pending register for each implemented level One bit position in each...

Page 797: ...ster is the result of a logical AND between the corresponding bits in the status and in the enable registers If a flag bit is set and the level enable bit is also set then the IRQ pending bit is set a...

Page 798: ...14 LSB 15 Field FLG 15 FLG 14 FLG 13 FLG 12 FLG 11 FLG 8 FLG 7 FLG 6 FLG 5 FLG 4 FLG 3 FLG 2 FLG 1 FLG 0 SRESET Undefined Addr 0x30 6C00 Figure 17 35 Interrupt Status Register MIOS14SR0 Table 17 35 MI...

Page 799: ...1 IRP0 SRESET 0000_0000_0000_0000 Addr 0x30 6C06 Figure 17 37 Interrupt Request Pending Register MIOS14RPR0 Table 17 37 MIOS14PR0 Bit Descriptions Bits Name Description 0 4 IRP15 1 1 Pending Bits MDAS...

Page 800: ...bus error if the bus error option is selected MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field EN 31 EN 30 EN 29 EN 28 EN 27 EN 24 EN 23 EN 22 EN 21 EN 20 EN 19 EN 18 EN 17 EN 16 SRESET 0000_0000_...

Page 801: ...he CPU is then informed as to which of the thirty two interrupt levels is requested Based on the interrupt level requested the software must determine which submodule requested the interrupt The softw...

Page 802: ...prescaling 50 ns cycle and with the maximum overall prescaling 32 s cycle For other fSYS clock cycle rates and prescaler choices the times mentioned in these paragraphs scale appropriately 17 13 1 MIO...

Page 803: ...signal to obtain the values for each edge When software attention is not needed for every pulse the interrupt can be disabled The software can read registers A and B2 coherently using a 32 bit read in...

Page 804: ...n Software can initialize the MIOS14 to generate both the rising and the falling edge of an output pulse With a MDASM pulses as narrow as 50 ns can be generated since software action is not needed bet...

Page 805: ...cycle can vary from one cycle to 64 Kbyte cycles The frequency can range from 0 48 Hz to 156 KHz though the resolution decreases at the higher frequencies to as low as seven bits The generation of out...

Page 806: ...ccumulation Counting the number of pulses on an input signal is another capability of the MIOS14 Pulse accumulation uses an MMCSM Since the counters in the counter submodules are software accessible p...

Page 807: ...ltiplexed through the PPM TPU3_A 16 channels TPU3_B 16 channels MIOS 12 PWM channels four MDA channels Internal GPIO 16 general purpose inputs 16 general purpose outputs Software configurable stream s...

Page 808: ...gister Name Address Usage S1 PPMMCR 0x30 5C00 Module Configuration Register T2 PPMTCR 0x30 5C02 Test Configuration Register S U3 PPMPCR 0x30 5C04 PPM Control Register S1 TX_CONFIG_1 0x30 5C06 TX Outpu...

Page 809: ...transmit and receive data in parallel Data is routed through the PPM using internal multiplexers Communication between the internal modules and the PPM remains a parallel connection but the PPM connec...

Page 810: ...data out of the PPM and which will receive data from the PPM The TX_CONFIG and RX_CONFIG registers allocate two bits to control each of the 16 internal multiplexers During transmit operations the TX_...

Page 811: ...nsmitted and received on PPM_TCLK cycles one PPM_TSYNC clock cycle defines a single 16 bit word transmit receive cycle The PPM can be configured to transfer data in one of two clock modes SPI and TDM...

Page 812: ...ata bits start to transmit on the falling edge of PPM_TSYNC In receive mode valid data starts to shift into RX_SHIFTER on the falling edge of PPM_TSYNC PPM_TSYNC stays low until the contents of TX_DAT...

Page 813: ...is a multiple of PPM_TCLK and is defined by the SAMP 0 2 field of the PPMPCR register For transmit operations the sample rate is the rate at which TX_DATA receives data from the internal modules For r...

Page 814: ...the sample rate with respect to the OP_16_8 bit setting For example if the PPM is transferring data on an 8 clock cycle then setting the sample rate to every 16 clocks will result in lost data In SPI...

Page 815: ...ouCAN is shorted with one or two other TouCAN modules C_TouCAN no longer has control of these signals and so they can be configured for another of the available functions Refer to Chapter 2 Signal Des...

Page 816: ...spectively The T2CLK signals can be shorted internally by SHORT_REG SH_T2CLK so that only one signal needs to be input to the device leaving the other signal free for PCS functionality 18 3 3 PPM Modu...

Page 817: ...ansmit or receive Clear PPMPCR STR if necessary 4 Set PPMMCR STOP When PPMMCR STOP is set the PPM module enters stop mode and the PPM module clocks will be stopped While in stop mode none of the PPM r...

Page 818: ...es per word TX_DATA 0 7 will transmit on PPM_TX1 TX_DATA 8 15 will transmit on PPM_TX_0 RX_SHIFTER 0 7 are received from PPM_RX1 RX_SHIFTER 8 15 are received from PPM_RX0 4 ENRX1 PPM Receive RX data e...

Page 819: ...s asserted while ENTX 1 the first data bit received will be the data that is transmitted from the PPM and not RX0 See Figure 18 10 To receive the first data frame correctly ENRX and ENTX should be set...

Page 820: ...Freescale Semiconductor Figure 18 10 Set ENRX While ENTX 1 Figure 18 11 Set ENTX while ENRX 1 ENRX PPM_TCLK PPM_TSYNC PPM_RX PPM_TX CH0 CH1 CH2 CH3 CH K CH2 CH3 CH0 CH K One Cycle CH0 1 1 ENTX PPM_TC...

Page 821: ...plexer that selects a 1 bit channel from an internal module to the PPM transmit data register See Table 18 6 for more information on channel control and setting the channel values Table 18 5 PPMPCR CM...

Page 822: ...o an internal module See Table 18 6 for more information on channel control and setting the channel values RX_CONFIG_1 and RX_CONFIG_2 can only be written while PPM receive mode is disabled PPMPCR ENR...

Page 823: ...ive Configuration Register 2 RX_CONFIG_2 Table 18 6 Configuration Register TX and RX Channel Settings TX RX_CONFIG Channel Number Channel Values 00 01 10 11 0 GPIO15 A_TPUCH0 B_TPUCH0 MPWM0 1 GPIO14 A...

Page 824: ...smitted serially shifted out on each PPM_TCLK cycle The data is shifted out least significant bit LSB first therefore TX_DATA15 first TX_DATA0 last 18 4 8 General Purpose Data Out GPDO GPDO is an inte...

Page 825: ...ls in the MPC561 MPC563 devices This feature allows functions whose internal signals are multiplexed on external signals to be accessible simultaneously MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 F...

Page 826: ...it settings for TPU shorting 5 Reserved 6 SH_ET1 Short ETRIG1 This bit enables an internal short between ETRIG1 and A_TPUCH15 0 Short disabled 1 Short ETRIG1 to A_TPUCH15 enabled 7 SH_ET2 Short ETRIG2...

Page 827: ...TouCAN_A A_CNRX0 A_CNTX0 All modules communicate via A_CNTX0 A_CNRX0 Table 18 9 SHORT_REG SH_TPU Bit Settings SH_TPU0 A_TPUCH0 B_TPUCH0 Effect on TPU3 Modules 1 Input Input Data on pad A_TPUCH0 will b...

Page 828: ...is enabled for any of these transmit data bits that bit will be transmitted for two PPM_TCLK cycles during its own bit time and the bit time of the following transmit data bit EXAMPLE If SHORT_CHx 1 t...

Page 829: ...ster Contents Comments Example 1 SHORT_CH_REG 0x0000 SHORT_CH 7 0 0x00 therefore no shorts enabled TX_DATA 0 15 0x1234 0b 0001 0010 0011 0100 Data transmitted 0x1234 Normal transmission Example 2 SHOR...

Page 830: ...TX_DATA 1 3 5 7 9 11 13 15 are enabled for re transmission TX_DATA 0 15 0x1234 0b 0001 0010 0011 0100 Underlines show bits to be re transmitted Data transmitted 0x303C 0b 0011 0000 0011 1100 Table 18...

Page 831: ...vention Consequently for each timer event the CPU setup and service times are minimized or eliminated The MPC561 MPC563 contains two independent TPU3s TPU_A and TPU_B These two TPU3 modules are memory...

Page 832: ...icrocode but are not directly available to the CPU The TCR1 clock is always derived from the system clock The TCR2 clock can be derived from the system clock or from an external input via theT2CLK clo...

Page 833: ...e TPU3 can also store information to be read by the CPU in the parameter RAM Detailed descriptions of the parameters required by each time function are beyond the scope of this manual Refer to the TPU...

Page 834: ...l from permanently blocking other functions other service requests of the same priority are performed in channel order after the lowest numbered highest priority channel is serviced i e round robin 19...

Page 835: ...interrupt level programmed in the IRL field of the TPU interrupt configuration register TICR Under the control of the ILBS bits in the ICR each interrupt request level is driven during one of four di...

Page 836: ...ivided by 1 2 4 or 8 depending on the value of the TCR1P field in the TPUMCR If the TPUMCR2 DIV2 bit is one the TCR1 counter increments at a rate of the internal clock divided by two If DIV2 is zero t...

Page 837: ...ocked preventing it from incrementing TCR2 When the external TCR2 pin is high TCR2 is incremented at the frequency of the DIV8 clock When T2CG is cleared an external clock from the TCR2 pin which has...

Page 838: ...within the 512 byte address space return zeros when read Table 19 6 shows the TPU3 address map Table 19 5 TCR2 Prescaler Control TCR2 Value Internal Clock Divide Ratio External Clock Divide Ratio TCR...

Page 839: ...3 for bit descriptions 0x30 4018 TPU_A 0x30 4418 TPU_B Host Service Request Register 0 HSRR0 See Table 19 14 for bit descriptions 0x30 401A TPU_A 0x30 441A TPU_B Host Service Request Register 1 HSRR1...

Page 840: ..._B Channel 6 Parameter Registers 0x30 4170 0x30 417F TPU_A 0x30 4570 0x30 457F TPU_B Channel 7 Parameter Registers 0x30 4180 0x30 418F TPU_A 0x30 4580 0x30 458F TPU_B Channel 8 Parameter Registers 0x3...

Page 841: ...10 Divide by 4 11 Divide by 8 Refer to Section 19 3 8 Prescaler Control for TCR1 for more information 3 4 TCR2P Timer Count Register 2 prescaler control TCR2 is clocked from the output of a prescaler...

Page 842: ...en developing custom TPU microcode 11 T2CSL TCR2 counter clock edge This bit and the T2CG control bit determine the clock source for TCR2 Refer to Section 19 3 9 Prescaler Control for TCR2 for details...

Page 843: ...Pin state MRL and TDL conditions of the new channel are latched as a result of a write CHAN register microinstruction 10 BP Breakpoint enable for microprogram counter PC 0 Breakpoint not enabled 1 Bre...

Page 844: ...PC register match with the PC breakpoint register PCBK is negated when the BKPT flag is cleared 10 CHBK Channel register breakpoint flag CHBK is asserted if a breakpoint occurs because of a CHAN regi...

Page 845: ...t level This three bit field specifies the interrupt request level for all channels This field is used in conjunction with the ILBS field to determine the request level of TPU3 interrupts 8 9 ILBS Int...

Page 846: ...er 0 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field CH 11 CH 10 CH 9 CH 8 SRESET 0000_0000_0000_0000 Addr 0x30 400E TPU_A 0x30 440E TPU_B Figure 19 11 CFSR1 Channel Function Select Register 1 MSB...

Page 847: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 Field CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 SRESET 0000_0000_0000_0000 Addr 0x30 4016 TPU_A 0x30 4416 TPU_B Figure 19 15 HSQR1 Host Sequence Register 1 Table...

Page 848: ...ing host service request field to one of three non zero states The CPU must monitor the host service request register until the TPU3 clears the service request to 0b00 before any parameters are change...

Page 849: ..._B Figure 19 20 CISR Channel Interrupt Status Register Table 19 17 CISR Bit Descriptions Bits Name Description 0 15 CH 15 0 Channel interrupt status 0 Channel interrupt not asserted 1 Channel interrup...

Page 850: ...ock frequency and minimum detectable pulses The reset value of these bits is zero defining the filter clock as four system clocks Refer to Table 19 20 14 T2CF T2CLK pin filter control When asserted th...

Page 851: ...once disable bit The PWOD bit does not lock the EPSCK field and the EPSCKE bit 0 Prescaler fields in MCR are write once 1 Prescaler fields in MCR can be written anytime 8 TCR2PSCK 2 TCR2 prescaler 2...

Page 852: ...22 SIUTST Bit Descriptions Bits Name Description 0 TPU_DBG This enables the test features of the TPU for use by TPU debuggers It should only be enabled while debugging TPU microcode 0 TPU debugging i...

Page 853: ...x30 415E A 0x30 455E B 6 0x30 4160 A 0x30 4560 B 0x30 4162 A 0x30 4562 B 0x30 4164 A 0x30 4564 B 0x30 4166 A 0x30 4566 B 0x30 4168 A 0x30 4568 B 0x30 416A A 0x30 456A B 0x30 416C A 0x30 456C B 0x30 41...

Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...

Page 855: ...The DPTRAM module is powered by VDD in normal operation The entire array may be used as standby RAM if standby power is supplied via the IRAMSTBY pin of the MPC561 MPC563 IRAMSTBY must be supplied by...

Page 856: ...ection is the array itself All DPTRAM module control and status registers are located in supervisor data space User read or write attempts will result in a bus error When the TPU3 is using the RAM arr...

Page 857: ...See Table 20 2 for bit descriptions 0x0100 Test 0x30 0002 Test Configuration Register DPTTCR 0x0000 Supervisor R W 0x30 0004 RAM Base Address Register RAMBAR See Table 20 3 for bit descriptions 0x0001...

Page 858: ...4 Stop Operation for more information 1 4 Reserved 5 MISF Multiple input signature flag MISF is readable at any time This flag bit should be polled by the host to determine if the MISC has completed r...

Page 859: ...he 11 high order bits of the 24 bit base address of the DPTRAM array This allows the array to be placed on a 8 Kbyte boundary anywhere in the memory map Do not overlap the DPTRAM array memory map with...

Page 860: ...r do they have any effect on the operation of the DPTRAM module 20 4 2 Standby Operation The DPTRAM array uses a separate power supply IRAMSTBY to provide power to the DPTRAM array during a power down...

Page 861: ...e system clock remains stopped until the STOP bit is cleared or the DPTRAM module is reset The STOP bit is initialized to logical zero during reset Only the STOP bit in the DPTMCR can be accessed whil...

Page 862: ...sed on the output of these reads MISC reads are performed when one of the TPU3 modules does not request back to back accesses to the DPTRAM provided that the MISEN bit in the DPTMCR is set The MISC ge...

Page 863: ...ck The primary function of the UC3F EEPROM module is to serve as electrically programmable and erasable NVM to store program instructions and or data It is a class of non volatile solid state silicon...

Page 864: ...ain small blocks Information is transferred to the UC3F EEPROM by long word 64 bits word 32 bits half word 16 bits or byte 8 bits To improve system performance each array read access retrieves 32 byte...

Page 865: ...data integrity and reliability 21 0 1 Features of the CDR3 Flash EEPROM UC3F High density single transistor Flash bit cell 40 to 125 C ambient temperature operating range 40 to 85 C on the suffix C de...

Page 866: ...solated from all other VDD pins inside the device The specified voltage range during operation is 2 6 V 0 1 V VSSF Ground Pin UC3F ground To reduce noise in the read path no other circuits should be c...

Page 867: ...The UC3F module control registers shown in Table 21 2 are selected with individual register selects generated from the BIU As such each Flash module that is designed using the UC3F EEPROM module may u...

Page 868: ...itten to 0 once after reset when UC3FCTL CSC 0 to allow protection of the write locked register bits after initialization WARNING If the lock protection mechanism is enabled LOCK 0 before PROTECT and...

Page 869: ...e is in uncensored mode 8 15 SUPV Supervisor space The SUPV bits are used to assign supervisor space restrictions for each block of the UC3F array The index for the SUPV bit field is used to determine...

Page 870: ...olled by the DATA bit corresponding to the array block containing that small block This particular small block is controlled by the appropriate SBDATA bit while the remainder of that array block is co...

Page 871: ...the host block of Small Block 0 are programmed and erased as if the two blocks are one large array block 64 Kbytes When SBEN 0 1 small block 0 and the residual block contained in the host block of sma...

Page 872: ...ram or erase sequence but the program and erase voltages are not applied to locations within the protected small block s 0 small block M is unprotected 1 small block M is protected 8 9 Reserved 10 15...

Page 873: ...e FLASHID field is read only and writes have no effect MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field HVS PEGOOD PEFI EPEE B0EM SBBLOCK HRESET 0 0 0 X1 X2 000_0000_0000 Addr 0x2F C808 16 17 18 19 20...

Page 874: ...EGOOD is valid and PEGOOD 0 PEFI is valid after HVS negates and prior to the assertion of EHV or negation of SES 0 Program operation failed if PEGOOD 0 1 Erase operation failed if PEGOOD 0 3 EPEE EPEE...

Page 875: ...CENSOR If CSC 1 then CENSOR is configured for setting if PE 0 or clearing if PE 1 When the CSC bit is set the following bits in the UC3FMCR register are write locked LOCK FIC ACCESS SUPV DATA and PRO...

Page 876: ...OCK CSC SBEN and PE bits 0 UC3F EEPROM not configured for program or erase operation 1 Configure UC3F EEPROM for program or erase operation 31 EHV Enable high voltage EHV can be asserted only after th...

Page 877: ...buffers the 32 bytes of data retrieved from the UC3F array core will not be transferred into either read page buffer The BIU is expected to contain page update logic for controlling the updating of th...

Page 878: ...nfiguration Note that with the exception of bit 20 the bits in the UC3FCFIG are identical to those in the USIU hard reset configuration word The reset state of UC3FCFIG is user programmable MSB 0 1 2...

Page 879: ...10 7 Global Boot Chip Select Operation for more information 0 Memory controller bank 0 is active and matches all addresses immediately after reset 1 Memory controller is not activated after reset 4 5...

Page 880: ...ration Word 1 The Flash shadow row does not contain a valid Reset Configuration Word 21 EN_COMP1 Enable compression This bit enables the operation of the MPC564 with compressed code See Table 4 4 22 E...

Page 881: ...the UC3F EEPROM by asserting the reset signal A reset is the highest priority operation for the UC3F EEPROM and terminates all other operations The UC3F EEPROM module uses reset to initialize registe...

Page 882: ...te read page buffer A data fetch from a read page buffer is an on page read operation Section 21 3 3 1 Array On Page Read Operation If the data is not contained in one of the read page buffers 32 byte...

Page 883: ...l from a logic 0 state to a logic 1 state and is a bulk operation performed on one block or multiple blocks of the UC3F array 21 3 6 1 Overview of Program Erase Operation The embedded hardware program...

Page 884: ...ock unless the programming operation specifically targets an address location within that block small block to program If BLOCK or SBBLOCK is not set to 1 no address locations in that corresponding bl...

Page 885: ...ing that location must be erased and reprogrammed before that block of the UC3F array may be used reliably 8 If more information needs to be programmed go to step 3 9 Write SES 0 in the UC3FCTL regist...

Page 886: ...Interlock Operation Programming writes are accepted so that data may be programmed These writes may be to any UC3F array location The location to be programmed is determined from the address initially...

Page 887: ...approximately once per millisecond may also cause program or erase timeouts and are not recommended 21 3 8 Erasing To modify the charge stored in an isolated element of the UC3F bit from a logic 0 sta...

Page 888: ...for the blocks to be erased 2 Write BLOCK 0 7 and SBBLOCK 0 1 to select the blocks to be erased PE 1 and SES 1 in the UC3FCTL register NOTE BLOCK 0 7 and SBBLOCK 0 1 in conjunction with SBEN 0 1 deter...

Page 889: ...e UC3F remains in state S2 S1 T1 Write SES 0 or a reset S3 T3 Hardware Interlock A successful write to any UC3F array location is the erase interlock write If the write is to a register the erase hard...

Page 890: ...ed to the UC3F array or shadow information words Reads to the array block or blocks targeted for erase return indeterminate data since only a partial erase operation has been performed The erase opera...

Page 891: ...module is re enabled the suspended program or erase operation may be resumed by writing the HSUS bit to a 0 NOTE While there should be no harmful side effects resulting from disabling the UC3F module...

Page 892: ...ording to Table 21 9 While the device remains in the uncensored mode ACCESS may be set to allow the device to enter censored mode and still access the UC3F array ACCESS may not be set while the device...

Page 893: ...accessed 1 ACCESS cannot be changed FIC can be set UC3F array cannot be accessed CENSOR 0 1 can be set CENSOR 0 1 cannot be cleared 2 ACCESS cannot be changed FIC can be set UC3F array can be accesse...

Page 894: ...CENSOR 0 1 1 Write PROTECT 0 7 0x00 to enable the entire array for erase If SBEN M 1 then SBPROTECT M must also be cleared to 0 2 Write BLOCK 0 7 0xFF CSC 1 PE 1 and SES 1 in the UC3FCTL register If S...

Page 895: ...register until HVS 0 6 Read the UC3FCTL register Confirm PEGOOD 1 7 Write EHV 0 in the UC3FCTL register 8 Write SES 0 and CSC 0 21 3 11 4 Switching The UC3F EEPROM Censorship There are three states o...

Page 896: ...T2 Set CENSOR 0 and CENSOR 1 3 Information censorship no censorship or unknown to cleared censorship T3 Clear CENSOR 0 1 This is done only while the entire UC3F array is erased 4 Cleared censorship t...

Page 897: ...s of CALRAM provide the data to the RPCU 22 1 Features Standard CALRAM features are listed below One clock accesses Two cycle access for power savings Byte half word 16 bits or word 32 bit read write...

Page 898: ...address 0x3F 8000 0x3F FFFF as shown in Figure 22 1 and Figure 22 2 In addition the module is assigned 16 32 bit register address spaces 12 implemented and four unimplemented registers The 12 impleme...

Page 899: ...the normal device power VDD is off portions of the CALRAM array can be powered by separate power supply sources IRAMSTBY as shown in Figure 22 3 thus allowing the data to be retained 0x38 0000 0x37 F...

Page 900: ...Operation The CALRAM module has the following modes of operation Reset One cycle Two cycle Standby Stop Overlay 0x3F 8000 0x3F 9000 0x3F A000 0x3F B000 0x3F C000 0x3F D000 0x3F E000 0x3F F000 0x3F FF...

Page 901: ...e to privilege violation or an attempt to access unimplemented portions of array or register space then the type of the error generated depends on whether the access generating the error was initiated...

Page 902: ...ls in the overlay region of the U bus Flash will be driven by the CALRAM on the L bus The CALRAM also indicates to the L2U to block the data from the Flash to be driven onto the L bus As far as the RC...

Page 903: ...0 CRAM_RBA4 and CRAM_RBA5 Overlay region 1 is partially mapped to a region in Flash as specified by the CRAM_RBA1 If the region size of 256 bytes is selected for overlay region 1 for example then the...

Page 904: ...d by the two CALRAM modules available in MPC561 MPC563 0x3F 8000 0x3F F000 0x3F F400 0x3F FC00 0x3F F800 0x3F FFFF Overlay 6 Overlay 2 Overlay 7 Overlay 3 Overlay Region 4 Kbyte 0x07 FFFF 0x00 0000 U...

Page 905: ...long as shown in Figure 22 7 regardless of the value programmed in the RGN_SIZE field These 32 bytes occupy contiguous address space in CALRAM for example from 0x3F FFE0 to 0x3F FFFF The remainder 4...

Page 906: ...regions when the CLPS bit is set for CALRAM in MPC561 MPC563 U bus Flash Non Overlay Region CALRAM Normal Array Access CALRAM Overlay Access U bus Flash L Bus CALRAM Array 28 Kbytes Overlay 7 Overlay...

Page 907: ...ity Priority is determined by the region number the highest priority assigned to the lowest region number The benefit from this priority feature is that by storing the parameters in eight overlay regi...

Page 908: ...nored completely by the CALRAM module 22 5 Programming Model The following section describes the CALRAM programmer s model The CALRAM has one register CRAMMCR for configuring the CALRAM array and one...

Page 909: ...ol Registers Address Register 0x38 0000 CRAMMCR 0x38 0004 for factory test 0x38 0008 CRAM_RBA0 0x38 000C CRAM_RBA1 0x38 0010 CRAM_RBA2 0x38 0014 CRAM_RBA3 0x38 0018 CRAM_RBA4 0x38 001C CRAM_RBA5 0x38...

Page 910: ...resides 0 CALRAM module in one cycle operation 1 CALRAM module in two cycle operation 3 19 Reserved 20 R0 Read only read write privilege If the data relocate DR bit is set in Machine Status Register M...

Page 911: ...ALRAM array may be placed in supervisor or unrestricted space This bit controls the highest 8 Kbyte block lowest address of CALRAM in the associated array Likewise S1 S2 and S3 control other three blo...

Page 912: ...igure 22 10 CALRAM Region Base Address Register CRAM_RBAx Table 22 5 CRAM_RBAx Bit Descriptions Bits Name Description 0 3 RGN_SIZ E These bits define the size of the overlay region See Table 22 6 for...

Page 913: ...enabled In this mode CALRAM allows eight programmable sections four to 512 bytes of the on chip U bus Flash memory module to be overlaid by sections of the CALRAM 0 CALRAM module overlay is disabled...

Page 914: ...tor MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ownership Trace Register SRESET 0000_0000_0000_0000 Addr 0x38 002C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field Ownership Trace Registe...

Page 915: ...erate in serial mode and show all fetch cycles on the external bus This mode is selected by programming the ISCT_SER instruction fetch show cycle control field in the I bus support control register IC...

Page 916: ...ce refer to Section 23 4 Development Port Forcing the CPU to show all fetch cycles marked with the program trace cycle attribute can be done either by asserting the VSYNC pin as mentioned above or by...

Page 917: ...ked with the indirect change of flow attribute Queue flush information1 1 Unless next clock VF 111 See below 101 Branch indirect taken rfi mtmsr isync and in some cases mtspr to CMPA F ICTRL ECR or DE...

Page 918: ...being issued In both cases the first instruction fetch after debug mode is marked with the program trace cycle attribute and therefore is visible externally 23 1 3 Sequential Instructions Marked as I...

Page 919: ...he program executed between the two events 23 1 4 1 Synchronizing the Trace Window to the CPU Internal Events The assertion negation of VSYNC is done using the serial interface implemented in the deve...

Page 920: ...re must take special care when trying to detect the assertion negation of VSYNC When VF 011 it is a VSYNC assertion negation report only if the previous VF pins value was one of the following values 0...

Page 921: ...e level of fetch show cycles generated by the CPU For information on the fetch show cycles control bits refer to Table 23 5 NOTE A cycle marked with the program trace cycle attribute is generated for...

Page 922: ...ur and that are handled by the RCPU when MSR RI is clear result in a non restartable machine state For more information refer to Section 3 13 4 Exceptions In general breakpoints are recognized in the...

Page 923: ...er than or equal and less than or equal are easily obtained from these four conditions for more information refer to Section 23 2 1 6 Generating Six Compare Types Using the AND OR logic structures in...

Page 924: ...AR breakpoint address register Key features of internal watchpoint and breakpoint support are Four I address comparators each supports equal not equal greater than less than Two L address comparators...

Page 925: ...points may operate either in masked mode or in non masked mode Both go to x and continue working modes are supported for the instruction breakpoints 23 2 1 1 Restrictions There are cases when the same...

Page 926: ...ize Byte Address 0x00000003 Data value greater than 0x07 and less than 0x0c Programming options One L address comparator 0x00000003 and program for equal One L data comparator 0x00000007 and program f...

Page 927: ...lowing figure illustrates this partially supported scenario Figure 23 2 Partially Supported Watchpoint Breakpoint Example 23 2 1 4 Context Dependent Filter The CPU can be programmed to either recogniz...

Page 928: ...are after the first instruction breakpoint match is ignored Load store breakpoints and all counter generated breakpoints instruction and load store are not affected by this mode 23 2 1 6 Generating Si...

Page 929: ...Programming Options IWP0 First instruction watchpoint Comparator A Comparators A B IWP1 Second instruction watchpoint Comparator B Comparator A B IWP2 Third instruction watchpoint Comparator C Compar...

Page 930: ...ant when operating in half word mode only four signals from each 32 bit comparator are significant When operating in word mode only two signals from each 32 bit comparator are significant From the new...

Page 931: ...ts Programming Options Name Description Instruction Events Programming Options L address Events Programming Options L data Events Programming Options LWP0 First Load store watchpoint IWP0 IWP1 IWP2 IW...

Page 932: ...Byte 1 eq lt Byte 2 eq lt Byte 3 eq lt eq lt eq lt eq lt eq lt add 30 31 Data Cycle Size Compare Size Valid 0 Valid 1 Valid 2 Valid 3 G H G H G H Instruction Watchpoints L watchpoint 0 L watchpoint 1...

Page 933: ...ion routine AFTER it executes this instruction Therefore the value of the counter inside the breakpoint exception routine equals ZERO 23 2 3 1 Trap Enable Programming The trap enable bits can be progr...

Page 934: ...to Section 23 3 1 1 Debug Mode Enable vs Debug Mode Disable The user can work in debug mode starting from reset or the CPU can be programmed to enter debug mode as a result of a predefined list of ev...

Page 935: ...the fly programming of the instruction breakpoint 2 Load store trap enable bits used for on the fly programming of the load store breakpoint 3 Non maskable breakpoint used to assert the non maskable...

Page 936: ...in the sense that it is possible to continue to run the regular program from the location where it entered the debug mode When in debug mode all instructions are fetched from the development port but...

Page 937: ...two possible working modes are defined debug mode enable and debug mode disable These working modes are selected only during reset See Figure 23 7 for BDM mode selection Debug mode is enabled by asser...

Page 938: ...When debug mode is disabled all development support registers see list in Table 23 14 are accessible to the supervisor code MSR PR 0 and can be used by a monitor debugger software However the processo...

Page 939: ...disabled The internal freeze signal is connected to all relevant internal modules These modules can be programmed to stop all operations in response to the assertion of the freeze signal Refer to Sect...

Page 940: ...As a result of this event the machine may enter a non restartable state for more information refer to Section 3 13 4 Exceptions The processor enters into the debug mode state when at least one of the...

Page 941: ...ccess the real memory system according to the cycle s address The data register of the development port is mapped as a special control register therefore it is accessed using mtspr and mfspr instructi...

Page 942: ...aving them when entering debug mode is not necessary 23 3 1 6 Exiting Debug Mode The rfi instruction is used to exit from debug mode in order to return to the normal processor operation and to negate...

Page 943: ...by external logic To be sure that the correct value is used internally When driven asynchronous synchronous with the system clock the data presented to DSDI must be stable a setup time before the ris...

Page 944: ...sed below in more detail 23 4 6 1 Development Port Shift Register The development port shift register is a 35 bit shift register Instructions and data are shifted into it serially from DSDI using DSCK...

Page 945: ...chronous or asynchronous with the system clock CLKOUT The development port allows the selection of two methods for clocking the serial transmissions The first method allows the transmission to occur w...

Page 946: ...bit on DSDI after detecting ready bit on DSDO when in debug mode The start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits DI DI DI N N 1 N 2 DO DO DO N N...

Page 947: ...10 bits long and only seven data bits will be shifted into the shift register These seven bits will be latched into the TECR A control bit determines whether the data is latched into the trap enable a...

Page 948: ...port is shown in Table 23 12 Valid data from CPU and CPU interrupt status cannot occur in trap enable mode Table 23 10 Trap Enable Data Shifted into Development Port Shift Register Start Mode Contro...

Page 949: ...nstruction before asserting ready This allows duplex operation of the serial port while allowing the port to control all transmissions from the external development tool After detecting this ready sta...

Page 950: ...be determined by the value of the response or data shifted out 23 4 6 10 Serial Data Out of Development Port The encoding of data shifted out of the development port shift register in debug mode throu...

Page 951: ...be a new instruction trap enable or command possibly the one that was in progress when the sequencing error occurred The interrupt occurred encoding is used to indicate that the CPU encountered an in...

Page 952: ...4 must be written to the general purpose register 30 To end a download procedure an end download procedure command should be issued to the debug port and then additional DATA transaction should be sen...

Page 953: ...signal 23 6 Development Support Registers Table 23 14 lists the registers used for development support in SPR number order and the register sections Section 23 6 2 Comparator A D Value Registers CMPA...

Page 954: ...Support Control Register ICTRL See Table 23 26 for bit descriptions 159 Breakpoint Address Register BAR See Table 23 28 for bit descriptions 630 Development Port Data Register DPDR See Section 23 6 1...

Page 955: ...esponding mask bit in the DER is set All bits are cleared to zero following reset Table 23 16 Development Support Registers Write Access Protection MSR PR Debug Mode Enable In Debug Mode Result 0 0 X...

Page 956: ...t exception is asserted 8 PRE Program exception bit Set when the program exception is asserted 9 FPUVE Floating point unavailable exception bit Set when the program exception is asserted 10 DECE Decre...

Page 957: ...a result of the assertion of an external breakpoint Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set 31 DPI Development port interrupt bit Set by the devel...

Page 958: ...0 Debug mode entry disabled reset value 1 Debug mode entry enabled 14 TRE Trace exception enable bit 0 Debug mode entry disabled 1 Debug mode entry enabled reset value 15 FPASEE Floating point assist...

Page 959: ...led reset value 31 DPIE Development port interrupt enable bit 0 Debug mode entry disabled 1 Debug mode entry enabled reset value MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field CNTV SRESET Unaffected...

Page 960: ...00_0000_0000_0000 Addr SPR 151 Figure 23 19 Breakpoint Counter B Value and Control Register COUNTB Table 23 21 Breakpoint Counter B Value and Control Register COUNTB Bits Name Description 0 15 CNTV Co...

Page 961: ...4 5 6 7 8 9 10 11 12 13 14 15 Field CTE CTF CTG CTH CRWE CRWF SRESET 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field CSG CSH SUSG SUSH CGBMSK CHBMSK UNUSED SRESET 0000_00...

Page 962: ...operating mode for comparator H 22 25 CGBMSK Byte mask for 1st L data comparator 0000 all bytes are not masked 0001 the last byte of the word is masked 1111 all bytes are masked 26 29 CHBMSK Byte mask...

Page 963: ...r E 01 match from comparator F 10 match from comparators E F 11 match from comparators E F 6 LW0LADC 1st L bus watchpoint care don t care L addr events 0 Don t care 1 Care 7 8 LW0LD 1st L bus watchpoi...

Page 964: ...arators G H 11 match from comparator G H 19 LW1LDDC 2nd L bus watchpoint care don t care L data events 0 Don t care 1 Care 20 BRKNOMSK Internal breakpoints non mask bit 0 masked mode breakpoints are r...

Page 965: ...ble 23 26 ICTRL Bit Descriptions Bits Mnemonic Description Function Non compressed mode1 Compressed Mode2 0 2 CTA Compare type of comparator A 0xx not active reset value 100 equal 101 less than 110 gr...

Page 966: ...x reset value 1 Ignore first match used for continue 29 31 ISCT_SER RCPU serialize control and Instruction fetch show cycle These bits control serialization and instruction fetch show cycles See Table...

Page 967: ...0 RCPU is not serialized normal mode and show cycles will be performed for all indirect changes in the program flow 1 11 RCPU is not serialized normal mode and no show cycles will be performed for fet...

Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...

Page 969: ...0 unlike the MPC500 standard MSB bit 0 and LSB bit 31 The bit description tables list the bit numbering and Nexus bit numbering 24 1 Features Summary The READI module is compliant with Class 3 of the...

Page 970: ...I message data in signals One MSEI message start end in signal One EVTI event in signal One RSTI reset in signal All features configurable and controllable via the auxiliary port Security features for...

Page 971: ...onfiguration is explained in Section 24 7 6 READI Reset Configuration U bus Snoop L bus Snoop L bus Master Data Trace Encoding Program Encoding Trace R W Access Control Registers Message Queues MDO 0...

Page 972: ...With 32 deep message queues throughput numbers were calculated for the following benchmark codes assuming full port mode For an example benchmark which had 10 9 direct branches 2 5 indirect branches 1...

Page 973: ...5 Data Read Synchronization Messaging 15 0x0F Watchpoint Message Refer to Section 24 12 1 Watchpoint Messaging 16 0x10 Auxiliary Access Device Ready for Upload Download Message Refer to Section 24 6 2...

Page 974: ...ch must be visible during the calibration or tuning process to enable accurate tuning of calibration constants Data Read Message DRM External visibility of data reads to internal memory mapped resourc...

Page 975: ...on other than a flow control instruction or isync Snooping Monitoring addresses driven by a bus master to detect the need for coherency actions Standard The phrase according to the standard implies ac...

Page 976: ...oad information register Data trace attributes register 1 Data trace attributes register 2 24 6 1 Register Map READI registers are accessible via the auxiliary port They can be classified into two cat...

Page 977: ...0_0000_0000 Addr 0x38 002C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 Field Current Task Process CTP HRESET 0000_0000_0000_0000 Figure 24 2 READI Ownership Trace Register OTR Table 24 4 OTR B...

Page 978: ...0 3 31 28 REV READI version number This field contains the revision level of the device 4 9 27 22 MDC1 1 The IEEE ISTO 5001 1999 defines these two fields as a single combined field READI Manufacturer...

Page 979: ...ce Messaging Enabled x1x DTM Data Trace Messaging Enabled xx1 OTM Ownership Trace Messaging Enabled 6 7 1 0 EC READI EVTI Control Field can be configured for synchronization and breakpoint generation...

Page 980: ...is bit as a 0 5 2 PTM The Program Trace Mode PTM bit enables an enhanced method of program trace This mode allows program trace to work with the ISCTL bits of the ICTRL register set to any value excep...

Page 981: ...er bits MSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field UBA RSTI 0000_0000_0011_1000 Addr 0x0D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 Field UBA RSTI 0000_0000_0010_1100 Figure 24 6 READI...

Page 982: ...Access Bit Descriptions RCPU Bits Nexus Bits Name Description 0 79 SC The start complete SC field is set when a read or write access is initiated The device will clear the SC bit once the read or writ...

Page 983: ...00 User Data 01 User Instruction 10 Supervisor Data 11 Supervisor Instruction 63 16 MAP The Map Select Field can be configured to allow access to multiple memory maps The primary processor memory map...

Page 984: ...to determine the status of the read or write access Refer to Table 24 13 and Table 24 14 for details 0 Read or write access has not been completed 1 Read or write access has completed NOTE The ERR fie...

Page 985: ...Zeros LS Byte ERR DV 16 bit Reserved Read as Zeros MS Byte LS Byte ERR DV 32 bit MS Byte LS Byte ERR DV Figure 24 9 RWD Field Configuration MSB 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field D...

Page 986: ...download request tool provides information and upload download information device tool provides information To write control or status to memory mapped locations the following sequence would be requi...

Page 987: ...tains read data This step is repeated until all data is read Refer to Section 24 10 Read Write Access for more details on read write access protocol 24 6 3 Accessing READI Tool Mapped Registers Via th...

Page 988: ...to ignore instruction show cycles so as to not impact U bus performance See Section 6 2 2 1 1 SIU Module Configuration Register SIUMCR To correctly trace program execution using BTM the READI module m...

Page 989: ...ploading OTM BTM DTM and Read Write Accesses External latching of MDO will occur on rising edge of MCKO Eight signals are implemented MDO 7 0 are used in full port mode MDO 1 0 are used in reduced por...

Page 990: ...emoved from the queue depends on the average message length the number of MDO signals and the MCKO clocking rate 24 7 3 Message Priority Message formatting is performed in the signal interface block T...

Page 991: ...ectively Fixed width fields can be concatenated before variable length fields without regard to the individual fields starting or ending at message N bit boundaries Variable width fields must end at m...

Page 992: ...rted Message Name Minimum Packet Size bits Maximu m Packet Size bits Packet Type Packet Description Direction Device ID 6 6 Fixed TCODE number 1 From Device 32 32 Fixed Device ID information Ownership...

Page 993: ...value 8 16 32 bits Error Message1 6 6 Fixed TCODE number 8 From Device 5 5 Fixed error code Program Trace Correction Message 6 6 Fixed TCODE number 10 0xA From Device 1 8 Variable correcting the numb...

Page 994: ...load Download Message 6 6 Fixed TCODE number 16 0x10 From Device Auxiliary Access Upload Request Message 6 6 Fixed TCODE number 17 0x11 From Tool 8 8 Fixed opcode to enable selected configuration stat...

Page 995: ...ce overrun1 00011 Read write access error 00100 Invalid message 00101 Invalid access opcode 00110 Watchpoint overrun 00111 Program data ownership trace overrun 01000 10111 Reserved 11000 11111 Vendor...

Page 996: ...6 Fixed Bit address 1 23 Variable Current instruction address Program Trace Direct Branch Synchronization Message With Compressed Code1 PTSM 1 6 6 Fixed TCODE number 60 0x3C From Device 1 8 Variable n...

Page 997: ...Min 1 NA 37 bits 8 bits Data Trace Data Write Message 5 Variable Max 25 Min 1 Variable Max 32 Min 8 NA 63 bits 15 bits Data Trace Data Read Message 6 Variable Max 25 Min 1 Variable Max 32 Min 8 NA 63...

Page 998: ...bits Auxiliary Access Upload Download Information Device Tool provides Information Message 19 0x13 Variable Max 80 Min 8 NA NA 86 bits 14 bits Resource Full Message6 27 0x1B Variable Max 4 Min 1 NA NA...

Page 999: ...nstance of a fixed length field followed by a variable field is a super field Figure 24 14 for example shows two super fields The only exception to Program Trace Direct Branch Synchronization Message...

Page 1000: ...ce messages 24 7 5 3 1 Example of Indirect Branch Message Table 24 23 illustrates an example of how the indirect branch public message is transmitted The example uses a 4 bit output port Note that T0...

Page 1001: ...he traces are monitored on the internal buses and these traces are captured as they occur and are sent out in the order they were captured and processed BTMs are in sequence and DTMs are in sequence h...

Page 1002: ...reset the READI control and status information and not three state the auxiliary output port Port size configuration is selected via the value of MDI0 at the negation of RSTI Table 24 25 describes the...

Page 1003: ...program In this user program If background debug mode BDM is enabled the ICTRL register cannot be modified through user program This register can only be accessed through the development port 4 DC reg...

Page 1004: ...0 while JCOMP RSTI is low EVTI low to enable Nexus 3 Negate JCOMP RSTI 4 If MDI 0 is high at JCOMP RSTI negation then full port mode is enabled otherwise Reduced mode is selected To exit READI mode 1...

Page 1005: ...es for Transmitting Input Messages An error message is sent out when an invalid TCODE is detected by the signal input formatter Refer to Section 24 10 8 2 Invalid Message for further details An error...

Page 1006: ...r address For some mispredicted branches and exception occurrences program trace correction messages correct the number of instructions since last taken branch as transmitted in prior BTM message 24 8...

Page 1007: ...d of the compressed instruction The program trace indirect branch with compressed code message has the format shown in Figure 24 21 The format of the bit address field is shown in Figure 24 22 The bit...

Page 1008: ...sent This is because a mispredicted branch is considered to be a sequential instruction Table 24 28 illustrates an example of a program trace correction message in case of an exception NOTE In case of...

Page 1009: ...because the tool is not aware that they occurred they were not transmitted out At Time 18 the Indirect Branch Message indicates that 3 sequential instructions were executed since trace correction this...

Page 1010: ...ODE 4 Number of sequential instructions executed since last taken branch 2 Unique portion of the target address 13 Sequential Instruction 14 Exception due to instruction at Time 8 Program Trace Correc...

Page 1011: ...VSYNC will be a synchronization message Program trace synchronization messages provide the full address without leading zeros and ensure that development tools fully synchronize with program trace re...

Page 1012: ...Figure 24 27 Indirect Branch Synchronization Message Format PTSM 1 24 8 2 4 3 Direct Branch Synchronization Message With Compressed Code For compressed code support six additional bits indicate the s...

Page 1013: ...31 Indirect Branch Synchronization Message Format with Compressed Code PTSM 1 Bit pointer format is shown in Figure 24 22 and bit address format is described in Table 24 26 24 8 2 4 5 Resource Full Me...

Page 1014: ...Addressing The relative address feature is compliant with the IEEE ISTO 5001 1999 recommendations and is designed to reduce the number of bits transmitted for addresses of indirect branch messages Th...

Page 1015: ...or message has the following format Figure 24 34 Error Message Queue Overflow Format 24 8 4 Branch Trace Message Operation 24 8 4 1 BTM Capture and Encoding Algorithm BTM is accomplished by capturing...

Page 1016: ...U Reference Manual 24 8 4 4 Instruction Flush Cases The various conditions under which the RCPU may signal instruction flushes of the RCPU prefetch queue or RCPU history buffer are 1 A taken branch di...

Page 1017: ...3 Number of Sequential Instructions since last taken branch 72 Don t care data idle clock 0001 Don t care data idle clock TCODE 4 Number of Sequential Instructions since last taken branch 4 Relative A...

Page 1018: ...ge TCODE 10 0xA Number of instructions corrected in trace 65 Don t care data idle clock MCKO MSEO MDO 7 0 01001010 00010000 00000000 TCODE 8 Error Code 0b00111 Program Data Ownership trace overrun Don...

Page 1019: ...Section 24 6 5 1 Program Trace Guidelines for further details TCODE 12 0xC Number messages cancelled 0 Full target address 0x654320 Don t care data idle clock MCKO MSEO MDO 7 0 00001100 00000000 00100...

Page 1020: ...ange and attributes This includes all RCPU initiated accesses and all L bus accesses L bus data cycles can have data sizes of 8 16 or 32 bits The READI module supports all three data sizes In full por...

Page 1021: ...a synchronization message Upon assertion of an event In EVTI signal If the READI module is not disabled at reset when EVTI asserts if the EC field is 0b00 in the DC register the next data trace messag...

Page 1022: ...the message queue to be flushed and an error message to be queued The error code within the error message indicates that a program data ownership trace overrun error has occurred The next DTM will be...

Page 1023: ...tion 24 6 1 9 Data Trace Attributes 1 and 2 Registers DTA1 and DTA2 respectively Data trace flow is depicted in Figure 24 49 Figure 24 49 Data Trace Flow Diagram for Non Pipelined Access Idle Data Rea...

Page 1024: ...nges then accesses to these off core MPC500 SPRs will be traced and the messages will not be distinguishable from accesses to normal memory map space Off core MPC500 SPRs typically exist in the 8 Kbyt...

Page 1025: ...ts Data field for data trace messages is 32 bits One idle clock between data trace messages 24 9 8 2 Throughput Calculations The data read or write trace message is 58 bits 6 TCODE 20 Relative address...

Page 1026: ...6 Data 0x1234 01000110 00101010 01110100 00110100 00010010 00000000 Don t care data idle clock TCODE 13 0xD Number of messages cancelled 0 Full target address 0x1468ACE Data 0xBE MCKO MSEO MDO 7 0 000...

Page 1027: ...ublic messages device ready for upload download upload request tool requests information download request tool provides information upload download information device tool provides information Read wr...

Page 1028: ...ale Semiconductor Figure 24 57 Write Register Message Figure 24 58 Read Write Response Message TCODE 18 Opcode 8 bits Max Length 94 bits 8 80 bits Register Value 6 bits Min Length 22 bits TCODE 19 Ret...

Page 1029: ...med via the auxiliary port 1 The tool confirms that the device is ready before transmitting download request public message TCODE 18 Download Request Public CNT 0 Decrement CNT No Read Write Message T...

Page 1030: ...ed to indicate that the write access is complete 24 10 2 2 Block Write Operation For a block write access to memory mapped locations the following sequence of operations need to be performed via the a...

Page 1031: ...download request public message TCODE 18 should not be used to write subsequent data to the UDI register Data written to the UDI register via download request message TCODE 18 is not used by the devi...

Page 1032: ...ite data 0xXXXXXXXX WD don t care Privilege user data instruction supervisor data instruction PRV Map select select memory map 0b0 MAP Access count non zero number to indicate block access CNT 3 Data...

Page 1033: ...is the target register 3 The upload download information public message TCODE 19 is transmitted to the tool along with the data read from the targeted register indicating that the device is ready for...

Page 1034: ...s is terminated at the boundary of the nearest completed access The resulting data is discarded and not written to the UDI If a new access has been programmed in the RWA register then that access will...

Page 1035: ...response is not deterministic 24 10 8 3 Invalid Access Opcode An error message is sent out when an invalid access opcode is received by READI The error code within the error message indicates that an...

Page 1036: ...and completely 24 10 10 1 Assumptions for Throughput Analysis All accesses are single read accesses only MCKI running at 28 MHz MCKO running at 56 MHz 56 MHz internal operation Five clock internal L b...

Page 1037: ...pped locations 64 Kbyte block Byte read access In 64 Kbyte Block Writes Per Second 61 61 95 95 Table 24 31 Throughput Comparison for FPM and RPM MDO MDI Configurations Access Type Reduced Port Mode 2...

Page 1038: ...Read Access Figure 24 65 Device Ready for Upload Download Request Message MSEI MSEO MDI MDO Download Request Message TCODE 18 Upload Download Information Message TCODE 19 Upload Download Information M...

Page 1039: ...load Request Message MCKI MSEI MDI 1 0 01 00 01 11 11 00 00 00 TCODE 17 0x11 Access Opcode 15 RWA register 0xE Don t care data idle clock Don t care data idle clock TCODE 18 0x12 Access Opcode 10 DC r...

Page 1040: ...not implemented Watchpoint setting via READI can only be done using the BDM protocol 24 12 1 Watchpoint Messaging The READI module provides watchpoint messaging using IEEE ISTO 5001 1999 defined publi...

Page 1041: ...t occurs multiple times before the first occurrence of that watchpoint has been messaged out The watchpoint message which has information of all the watchpoints that occurred prior to the detection of...

Page 1042: ...trace provides a macroscopic view such as task flow reconstruction when debugging software written in a high level or object oriented language It offers the highest level of abstraction for tracking...

Page 1043: ...or code within the error message indicates that a program data ownership trace overrun error has occurred Refer to Table 24 20 The error message has the following format Figure 24 75 Error Message For...

Page 1044: ...ams Figure 24 76 Ownership Trace Message Figure 24 77 Error Message Program Data Ownership Trace Overrun 24 14 RCPU Development Access This section details the RCPU development access support features...

Page 1045: ...On the MPC561 MPC563 the BDM signals are shared with the READI signals Therefore BDM access is limited to access via the Nexus vendor defined development support messages Figure 24 78 RCPU Developmen...

Page 1046: ...s header followed by 7 or 32 bits of data instruction depending on the RCPU development port mode The three status bits in the DSDO data indicates if the device is ready to receive the next message fr...

Page 1047: ...ess the protocol for transmission of development serial data in DSDI and out DSDO is performed through the IEEE ISTO 5001 1999 compliant vendor defined messages After enabling RCPU development access...

Page 1048: ...ee ways to enter debug mode provided debug mode has been enabled 1 Enter debug mode halted state out of system reset through READI module configuration This is displayed in Figure 24 84 2 Enter debug...

Page 1049: ...ESET GENERIC RCPU DEVELOPMENT PROTOCOL Tool Asserts HRESET Tools Negates HRESET 16 clocks after receiving Device Ready negation to enter debug mode negation to NOT enter debug mode DOR 1 Yes Yes Debug...

Page 1050: ...READI will take approximately 10 clocks to decode the DSDI data message After the message has been decoded READI will take 35 clocks to serially shift in the 35 bits of DSDI data to the RCPU developme...

Page 1051: ...after ready msg SRESET is negated by the MCU HRESET at least 16 Dev ID Message 1 3 DSDI msg USIU drives Tool drives after some internal system clocks delay Tool drives BDM is set based on READI and BD...

Page 1052: ...o CPU 1 1 0 Trap enable Does not exist Transfer data to Trap Enable Control Register 1 1 1 0011111 Does not exist Negate breakpoint requests to the CPU 1 1 1 0 Does not exist NOP Table 24 34 Developme...

Page 1053: ...ode 0b00100 Invalid Message Don t care data idle clock MCKO MSEO MDO 7 0 00001000 00000001 00000000 MCKI MSEI MDI 1 0 00 10 11 11 11 10 11 11 00 Don t care data idle clock TCODE 56 0x38 Header Start 1...

Page 1054: ...will be held negated Low power mode entry for the MCU will be held off until the READI module has transmitted all existing messages in the queues and transmit buffers During this time input messages...

Page 1055: ...e in all but two areas listed below Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committe...

Page 1056: ...563 implementation includes a TAP controller a 4 bit instruction register and two test registers a one bit bypass register and a 427 bit MPC563 or 423 bit MPC561 boundary scan register This implementa...

Page 1057: ...hown in Figure 25 3 NOTE JTAG puts all output pins in fast slew rate mode Enough current cannot be supplied to allow all the pins to be switched simultaneously so this should be avoided Figure 25 3 JT...

Page 1058: ...troller State Machine 25 1 2 2 Boundary Scan Register The MPC561 MPC563 scan chain implementation has a 427 bit MPC563 or 423 bit MPC561 boundary scan register This register contains bits for most dev...

Page 1059: ...2 displays boundary scan bit definitions for the MPC563 Table 25 1 MPC561 Boundary Scan Bit Definition BSDL Bit Cell Type Pin Port Name BSDL Function Safe Valu e Contro l Cell Disable Value Disable R...

Page 1060: ...IO 5vsa 42 BC_2 controlr 0 43 BC_7 A_TPUCH1 bidir 0 42 0 Z IO 5vsa 44 BC_2 controlr 0 45 BC_7 A_TPUCH2 bidir 0 44 0 Z IO 5vsa 46 BC_2 controlr 0 47 BC_7 A_TPUCH3 bidir 0 46 0 Z IO 5vsa 48 BC_2 contro...

Page 1061: ...controlr 0 79 BC_7 A_AN3_ANZ_PQB3 bidir 0 78 0 Z IO 5vsa 80 BC_2 controlr 0 81 BC_7 A_AN48_PQB4 bidir 0 80 0 Z IO 5vsa 82 BC_2 controlr 0 83 BC_7 A_AN49_PQB5 bidir 0 82 0 Z IO 5vsa 84 BC_2 controlr 0...

Page 1062: ...BC_2 controlr 0 115 BC_7 B_AN49_PQB5 bidir 0 114 0 Z IO 5vsa 116 BC_2 controlr 0 117 BC_7 B_AN50_PQB6 bidir 0 116 0 Z IO 5vsa 118 BC_2 controlr 0 119 BC_7 B_AN51_PQB7 bidir 0 118 0 Z IO 5vsa 120 BC_2...

Page 1063: ...C_2 controlr 0 151 BC_7 MDA27 bidir 0 150 0 Z IO 5vsa 152 BC_2 controlr 0 153 BC_7 MDA28 bidir 0 152 0 Z IO 5vsa 154 BC_2 controlr 0 155 BC_7 MDA29 bidir 0 154 0 Z IO 5vsa 156 BC_2 controlr 0 157 BC_7...

Page 1064: ...86 BC_2 controlr 0 187 BC_7 MPIO32B10_PPM_TSYNC bidir 0 186 0 Z IO 26v5vs 188 BC_2 controlr 0 189 BC_7 MPIO32B11_C_CNRX0 bidir 0 188 0 Z IO 5vfa 190 BC_2 controlr 0 191 BC_7 MPIO32B12_C_CNTX0 bidir 0...

Page 1065: ...IO 5vfa 220 BC_2 controlr 0 221 BC_7 MISO_QGPIO4 bidir 0 220 0 Z IO 5vh 222 BC_2 controlr 0 223 BC_7 MOSI_QGPIO5 bidir 0 222 0 Z IO 5vh 224 BC_2 controlr 0 225 BC_7 SCK_QGPIO6 bidir 0 224 0 Z IO 5vh...

Page 1066: ...BC_7 DATA_SGPIOD18 bidir 0 255 0 Z IO 26v5vs 257 BC_2 controlr 0 258 BC_7 DATA_SGPIOD14 bidir 0 257 0 Z IO 26v5vs 259 BC_2 controlr 0 260 BC_7 DATA_SGPIOD15 bidir 0 259 0 Z IO 26v5vs 261 BC_2 controlr...

Page 1067: ..._2 controlr 0 292 BC_7 DATA_SGPIOD26 bidir 0 291 0 Z IO 26v5vs 293 BC_2 controlr 0 294 BC_7 DATA_SGPIOD27 bidir 0 293 0 Z IO 26v5vs 295 BC_2 controlr 0 296 BC_7 DATA_SGPIOD4 bidir 0 295 0 Z IO 26v5vs...

Page 1068: ..._2 controlr 0 328 BC_7 ADDR_SGPIOA23 bidir 0 327 0 Z IO 26v5vs 329 BC_2 controlr 0 330 BC_7 ADDR_SGPIOA22 bidir 0 329 0 Z IO 26v5vs 331 BC_2 controlr 0 332 BC_7 ADDR_SGPIOA30 bidir 0 331 0 Z IO 26v5vs...

Page 1069: ...362 BC_7 ADDR_SGPIOA12 bidir 0 361 0 Z IO 26v5vs 363 BC_2 controlr 0 364 BC_7 BI_B_STS_B bidir 0 363 0 Z IO 26v 365 BC_2 controlr 0 366 BC_7 BURST_B bidir 0 365 0 Z IO 26v 367 BC_2 controlr 0 368 BC_7...

Page 1070: ...26v 401 BC_2 controlr 0 402 BC_7 BG_B_VF0_LWP1 bidir 0 401 0 Z IO 26v 403 BC_2 controlr 0 404 BC_7 BB_B_VF2_IWP3 bidir 0 403 0 Z IO 26v 405 BC_2 controlr 0 406 BC_7 SGPIOC7_IRQOUT_B_LWP 0 bidir 0 405...

Page 1071: ...controlr 0 5 BC_7 B_TPUCH0 bidir 0 4 0 Z IO 5vsa 6 BC_2 controlr 0 7 BC_7 B_TPUCH1 bidir 0 6 0 Z IO 5vsa 8 BC_2 controlr 0 9 BC_7 B_TPUCH2 bidir 0 8 0 Z IO 5vsa 10 BC_2 controlr 0 11 BC_7 B_TPUCH3 bi...

Page 1072: ...ontrolr 0 41 BC_7 A_TPUCH0 bidir 0 40 0 Z IO 5vsa 42 BC_2 controlr 0 43 BC_7 A_TPUCH1 bidir 0 42 0 Z IO 5vsa 44 BC_2 controlr 0 45 BC_7 A_TPUCH2 bidir 0 44 0 Z IO 5vsa 46 BC_2 controlr 0 47 BC_7 A_TPU...

Page 1073: ...2_ANY_PQB2 bidir 0 76 0 Z IO 5vsa 78 BC_2 controlr 0 79 BC_7 A_AN3_ANZ_PQB3 bidir 0 78 0 Z IO 5vsa 80 BC_2 controlr 0 81 BC_7 A_AN48_PQB4 bidir 0 80 0 Z IO 5vsa 82 BC_2 controlr 0 83 BC_7 A_AN49_PQB5...

Page 1074: ...C_7 B_AN48_PQB4 bidir 0 112 0 Z IO 5vsa 114 BC_2 controlr 0 115 BC_7 B_AN49_PQB5 bidir 0 114 0 Z IO 5vsa 116 BC_2 controlr 0 117 BC_7 B_AN50_PQB6 bidir 0 116 0 Z IO 5vsa 118 BC_2 controlr 0 119 BC_7 B...

Page 1075: ...9 BC_7 MDA15 bidir 0 148 0 Z IO 5vsa 150 BC_2 controlr 0 151 BC_7 MDA27 bidir 0 150 0 Z IO 5vsa 152 BC_2 controlr 0 153 BC_7 MDA28 bidir 0 152 0 Z IO 5vsa 154 BC_2 controlr 0 155 BC_7 MDA29 bidir 0 15...

Page 1076: ...0 184 0 Z IO 5vsa 186 BC_2 controlr 0 187 BC_7 MPIO32B10_PPM_TSYNC bidir 0 186 0 Z IO 26v5vs 188 BC_2 controlr 0 189 BC_7 MPIO32B11_C_CNRX0 bidir 0 188 0 Z IO 5vfa 190 BC_2 controlr 0 191 BC_7 MPIO32...

Page 1077: ...idir 0 218 0 Z IO 5vh 220 BC_2 controlr 0 221 BC_7 MISO_QGPIO4 bidir 0 220 0 Z IO 5vh 222 BC_2 controlr 0 223 BC_7 MOSI_QGPIO5 bidir 0 222 0 Z IO 5vh 224 BC_2 controlr 0 225 BC_7 SCK_QGPIO6 bidir 0 22...

Page 1078: ...6 bidir 0 255 0 Z IO 26v5vs 257 BC_2 controlr 0 258 BC_7 DATA_SGPIOD17 bidir 0 257 0 Z IO 26v5vs 259 BC_2 controlr 0 260 BC_7 DATA_SGPIOD18 bidir 0 259 0 Z IO 26v5vs 261 BC_2 controlr 0 262 BC_7 DATA_...

Page 1079: ...C_2 controlr 0 292 BC_7 DATA_SGPIOD6 bidir 0 291 0 Z IO 26v5vs 293 BC_2 controlr 0 294 BC_7 DATA_SGPIOD7 bidir 0 293 0 Z IO 26v5vs 295 BC_2 controlr 0 296 BC_7 DATA_SGPIOD26 bidir 0 295 0 Z IO 26v5vs...

Page 1080: ...2 controlr 0 328 BC_7 ADDR_SGPIOA28 bidir 0 327 0 Z IO 26v5vs 329 BC_2 controlr 0 330 BC_7 ADDR_SGPIOA24 bidir 0 329 0 Z IO 26v5vs 331 BC_2 controlr 0 332 BC_7 ADDR_SGPIOA23 bidir 0 331 0 Z IO 26v5vs...

Page 1081: ...GPIOA13 bidir 0 361 0 Z IO 26v5vs 363 BC_2 controlr 0 364 BC_7 ADDR_SGPIOA11 bidir 0 363 0 Z IO 26v5vs 365 BC_2 controlr 0 366 BC_7 ADDR_SGPIOA12 bidir 0 365 0 Z IO 26v5vs 367 BC_2 controlr 0 368 BC_7...

Page 1082: ...T1 output2 1 O 26v 401 BC_2 internal 1 402 BC_2 WE_B_AT0 output2 1 O 26v 403 BC_2 controlr 0 404 BC_7 BR_B_VF1_IWP2 bidir 0 403 0 Z IO 26v 405 BC_2 controlr 0 406 BC_7 BG_B_VF0_LWP1 bidir 0 405 0 Z IO...

Page 1083: ...These pins are used in the reset configuration to enter JTAG Board level connections to them will not be testable with the EXTEST and CLAMP instructions They do respond to the HI Z JTAG instruction f...

Page 1084: ...control cell that is associated with this data cell and can disable its output Column 7 The disable value column gives the value that must be scanned into the control cell identified by the previous...

Page 1085: ...will appear on the outputs when entering the EXTEST instruction The SAMPLE PRELOAD instruction also provides a means to obtain a snapshot of system data and control signals NOTE Since there is no inte...

Page 1086: ...t state to either enter or remain in the low power stop mode Leaving the TAP controller in the test logic reset state negates the ability to achieve low power but does not otherwise affect device func...

Page 1087: ...EE 1149 1 Compliant Interface JTAG MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor 25 33 25 2 2 BSDL Description The BSDL file for the MPC561 MPC563 can be found on the Freescale web si...

Page 1088: ...IEEE 1149 1 Compliant Interface JTAG MPC561 MPC563 Reference Manual Rev 1 2 25 34 Freescale Semiconductor...

Page 1089: ...sion unit key features Instruction code on line decompression is based on an instruction class algorithm There is no need for address translation between compressed and non compressed address spaces I...

Page 1090: ...nal branch displacement is up to 4 Kbytes Unconditional branch displacement is up to 4 Mbytes NOTE Branch displacement is hardware limited The compiler can enlarge the branch scope by creating branch...

Page 1091: ...es A 4 bit class identifier is added to the beginning of each compressed instruction to supply class identification during decompression Compressed and bypass field lengths may vary A fully bypassed i...

Page 1092: ...he bit pointer into the IP field of issued compressed branch target address The branch compressed target base address is calculated according the direct branch addressing mode If a branch has absolute...

Page 1093: ...ranch instruction BEFORE compression mapping Conditional immediate branch instruction AFTER compression mapping B form Branch target compressed address 4 biit Pointer 4 bit Pointer 4 bit Pointer Word...

Page 1094: ...any change from one of the following RCPU registers LR CTR SRR0 See the RCPU User s Manual for more details These registers should contain or be loaded by the 32 bit compressed address of existing co...

Page 1095: ...be 2 to 9 bits long Vocabulary table pointers are reversed in the code This means the pointer s LSB will be the first bit In a class with a single segment of full compression data is fetched from both...

Page 1096: ...uction The bypassed segment is16 zero bits This bypass is coded by a value of 11 0xB in the TP2LEN field of the DCCR register A 2 9 Instruction Class Structures and Programming The four possible compr...

Page 1097: ...the 16 LSBs of the decompressed instruction A 2 9 3 Twin Segment Full Compression CLASS_2 This MPC562 MPC564 instruction is divided into two segments Each segment is compressed and mapped into a diff...

Page 1098: ...is programmable The right segment is either fully bypassed by a 16 bit field or by a shorter field which is decompressed according to fixed rules Figure A 9 CLASS_3 Instruction Layout The definition o...

Page 1099: ...cess to the vocabulary in RAM 1 or RAM 2 respectively When the vocabulary is located in RAM 1 the class is referred to as CLASS_4band when the vocabulary is located in RAM 2 the class is referred to a...

Page 1100: ...et Thus maximum branch offsets in decompression on mode are reduced The RCPU uses the word offset for direct branch target address computation The RCPU provides the instruction pointer portion of the...

Page 1101: ...ression off mode If the chip wakes up with decompression disabled the initialization routine can be executed at any time before entering decompression on mode After the compression environment is init...

Page 1102: ...e MSR register when the rfi instruction is executed Bit 29 is the DCMPEN bit of the MSR The next step is to load SRR0 with a target address in compressed non compressed format and then executing an rf...

Page 1103: ...COF RCPU access only are forwarded by the BIU along with the U bus access Additional information about the IP of the compressed instruction address is provided on the U bus data bus Refer below to Se...

Page 1104: ...compressed code see Chapter 24 READI Module BBCMCR DECOMP_SC_EN should not be set if there is no intention to use compressed code as it will degrade U bus performance The show cycle may be delayed by...

Page 1105: ...or C 11 match from comparators C D 18 19 IWP3 I bus 4th watchpoint programming 0x not active reset value 10 match from comparator D 11 match from comparators C D 0x not active reset value 10 match fro...

Page 1106: ...n fetch show cycles See Table A 2 for the bit definitions NOTE Changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ICTRL 1...

Page 1107: ...accesses do not affect the DCCR0 register The DCCR0 register will always return 0x0000 0000 when read MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field TP1LEN TP2LEN TP1BA TP2BA Reset Unaffected Addr D...

Page 1108: ...bits 0x5 TP2 length is 5 bits 0x6 TP2 length is 6 bits 0x7 TP2 length is 7 bits 0x8 TP2 length is 8 bits 0x9 TP2 length is 9 bits 0xA Reserved 0xB TP2 field is a 0 bit compact bypass field 0xC TP2 fie...

Page 1109: ...ries Twin Segments Full Compression CLASS 2a 1 2 1 V1 2 V2 0 X1 X2 Twin Segments Full Compression With Swapped Vocabularies Vocabulary In RAM 2 For MSB Segment CLASS 2b V2 V1 1 X2 X1 Left Segment Comp...

Page 1110: ...MPC562 MPC564 Compression Features MPC561 MPC563 Reference Manual Rev 1 2 A 22 Freescale Semiconductor...

Page 1111: ...sh Control Registers EEPROM UC3F Table B 7 DPTRAM Control Registers Table B 8 DPTRAM Memory Arrays Table B 9 Time Processor Unit 3 A and B TPU3 A and B Table B 10 QADC64E A and B Queued Analog to Digi...

Page 1112: ...ster See Table 3 5 for bit descriptions 32 MSR S MSR Machine State Register See Table 3 11 for bit descriptions 32 SPR 1 U XER Integer Exception Register See Table 3 10 for bit descriptions 32 SPR 8 U...

Page 1113: ...e Register See Table 23 23 for bit descriptions 32 SPR 156 D S LCTRL1 L bus Support Control Register 1 See Table 23 24 for bit descriptions 32 S SPR 157 D S LCTRL2 L bus Support Control Register 2 See...

Page 1114: ...for bit descriptions 32 SPR 792 795 S L2U_RBAx L2U Region x Base Address Register See Table 11 8 for bit descriptions 32 SPR 816 819 S MI_RAx MI Region x Attribute Register See Table 4 6 for bit descr...

Page 1115: ...Decompressor Class Configuration Register See Table A 3 for bit descriptions 32 0x2F A02C S DCCR11 Decompressor Class Configuration Register See Table A 3 for bit descriptions 32 0x2F A030 S DCCR12 D...

Page 1116: ...egister See Table 6 25 for bit descriptions 32 H 0x2F C030 U EMCR External Master Mode Control Register See Table 6 13 for bit descriptions 32 H 0x2F C038 U PDMCR2 Pads Module Configuration Register 2...

Page 1117: ...STAT Memory Status See Table 10 7 for bit descriptions 16 H System Integration Timers 0x2F C200 U3 TBSCR Time Base Status and Control See Table 6 18 for bit descriptions 16 H 0x2F C204 U3 TBREF0 Time...

Page 1118: ...bit descriptions 16 U 0x2F C294 0x2F C2FC Reserved System Integration Timer Keys 0x2F C300 U TBSCRK Time Base Status and Control Key See Table 8 8 for bit descriptions 32 POR 0x2F C304 U TBREF0K Time...

Page 1119: ...ey register see Section 8 8 3 2 Keep Alive Power Registers Lock Mechanism 4 Locked after Power on Reset POR A write of 0x55CCAA33 must performed to the key register to unlock See Section 8 8 3 2 Keep...

Page 1120: ...Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 EMU of either TPUMCR_A or TPUMCR_B is set DPTRAM DPTRAM Memory Array 16 Table B 9 Time Processor Unit 3 A and B TPU3 A and B Addr...

Page 1121: ...S M 0x30 4020 S CISR_A TPU3_A Channel Interrupt Status Register See XrefBlue Table 19 17 for bit descriptions 16 S M 0x30 4022 T LR_A TPU3_A Link Register4 162 S M 0x30 4024 T SGLR_A TPU3_A Service G...

Page 1122: ...0x30 41EF S U3 TPU3_A Channel 14 Parameter Registers See Section 19 4 15 for more information 16 322 0x30 41F0 0x30 41FF S U3 TPU3_A Channel 15 Parameter Registers See Section 19 4 15 for more inform...

Page 1123: ...0 0x30 451F S U3 TPU3_B Channel 1 Parameter Registers 16 322 0x30 4520 0x30 452F S U3 TPU3_B Channel 2 Parameter Registers 16 322 0x30 4530 0x30 453F S U3 TPU3_B Channel 3 Parameter Registers 16 322 0...

Page 1124: ...egister Size Reset QADC_A Note Bit descriptions apply to QADC_B as well 0x30 4800 S QADC64MCR_A QADC64 Module Configuration Register See Table 13 5 and Table 14 5 for bit descriptions 16 S 0x30 4802 S...

Page 1125: ...ee Section 13 3 10 and Section 14 3 10 for bit descriptions 16 X QADC_B 0x30 4C00 S QADC64MCR_B QADC64 Module Configuration Register 16 S 0x30 4C02 T QADC64TEST_ B QADC64 Test Register 16 0x30 4C04 S...

Page 1126: ...it descriptions 16 S 0x30 500A S U SCC1R1 SCI1 Control Register 1 See Table 15 25 for bit descriptions 16 S 0x30 500C S U SC1SR SCI1 Status Register See Table 15 26 for bit descriptions 16 S 0x30 500E...

Page 1127: ...0x30 504C 0x30 506A S U SCRQ Receive Queue Locations 16 S 0x30 506C 0x30 513F Reserved 0x30 5140 0x30 517F S U RECRAM Receive Data RAM 16 S 0x30 5180 0x30 51BF S U TRAN RAM Transmit Data RAM 16 S 0x3...

Page 1128: ...Table 18 10 for bit descriptions 16 S 0x30 5C2A S U SCALE_TCLK_REG Scale Transmit Clock Register See Table 18 13 for bit descriptions 16 S Table B 13 MIOS14 Modular Input Output Subsystem Address Acc...

Page 1129: ...ter See Table 17 28 for bit descriptions 16 S 0x30 601E S U MPWMSCR MPWMSM3 Status Control Register See Table 17 29 for bit descriptions 16 S MPWMSM4 MIOS Pulse Width Modulation Submodule 4 0x30 6020...

Page 1130: ...M8 MIOS Modulus Counter Submodule 8 0x30 6040 S U MMCSMCNT MMCSM8 Up Counter Register See Table 17 10 for bit descriptions 16 X 0x30 6042 S U MMCSMML MMCSM8 Modulus Latch Register See Table 17 11 for...

Page 1131: ...30 6078 S U MDASMAR MDASM15 DataA Register See Table 17 19 for bit descriptions 16 S 0x30 607A S U MDASMBR MDASM15 DataA Register See Table 17 19 for bit descriptions 16 S 0x30 607E S U MDASMSCR MDASM...

Page 1132: ...t descriptions 16 S MPWMSM19 MIOS Pulse Width Modulation Submodule 19 0x30 6098 S U MPWMPERR MPWMSM19 Period Register See XrefBlue Table 17 26 for bit descriptions 16 S 0x30 609A S U MPWMPULR MPWMSM19...

Page 1133: ...0 S U MMCSMCNT MMCSM22 Up Counter Register See XrefBlue Table 17 10 for bit descriptions 16 X 0x30 60B2 S U MMCSMML MMCSM22 Modulus Latch Register See XrefBlue Table 17 11 for bit descriptions 16 S 0x...

Page 1134: ...8 0x30 60E0 S U MDASMAR MDASM28 DataA Register See XrefBlue Table 17 19 for bit descriptions 16 S 0x30 60E2 S U MDASMBR MDASM28 DataA Register See XrefBlue Table 17 19 for bit descriptions 16 S 0x30 6...

Page 1135: ...ptions 16 S 0x30 6102 S U MPIOSMDDR MPIOSM Data Direction Register See XrefBlue Table 17 34 for bit descriptions 16 S MBISM MIOS Bus Interface Submodule 0x30 6800 S U MIOS14TPCR MIOS14 Test and Pin Co...

Page 1136: ...descriptions 16 S 0x30 6C70 S U MIOS14LVL1 MIOS14 Interrupt Level 1 Register See Table 17 43 for bit descriptions 16 X 1 Only bits WEN TEST STB and WIP affected by reset Table B 14 TouCAN A B and C CA...

Page 1137: ...for bit descriptions 32 S 0x30 709C 0x30 709E Reserved 0x30 70A0 S U ESTAT_A TouCAN_A Error and Status Register See Table 16 23 for bit descriptions 16 S 0x30 70A2 S U IMASK_A TouCAN_A Interrupt Mask...

Page 1138: ...st Register 16 S 0x30 7484 S CANICR_B TouCAN_B Interrupt Configuration Register 16 S 0x30 7486 S U CANCTRL0_B CANCTRL1_B TouCAN_B Control Register 0 TouCAN_B Control Register 1 16 S 0x30 7488 S U PRES...

Page 1139: ...5 U 0x30 7560 0x30 756F S U MBUFF6_B1 TouCAN_B Message Buffer 6 U 0x30 7570 0x30 757F S U MBUFF7_B1 TouCAN_B Message Buffer 7 U 0x30 7580 0x30 758F S U MBUFF8_B1 TouCAN_B Message Buffer 8 U 0x30 7590...

Page 1140: ...ask High 32 S 0x30 789A S U RX15MSKLO_C TouCAN_C Receive Buffer 15 Mask Low 32 S 0x30 789C 0x30 789E Reserved 0x30 78A0 S U ESTAT_C TouCAN_C Error and Status Register 16 S 0x30 78A2 S U IMASK_C TouCAN...

Page 1141: ...served and may cause a RCPU exception if read 2 See Table 16 3 and Table 16 4 for message buffer definitions Table B 15 UIMB U Bus to IMB Bus Interface Address Access Symbol Register Size Reset 0x30 7...

Page 1142: ...1 User Mapped Register OTR for more information 32 H 1 See Section 22 5 2 CALRAM Region Base Address Registers CRAM_RBAx for more information 2 This register is write only Table B 17 CALRAM Array Addr...

Page 1143: ...butes Register 1 See Table 24 15 for bit descriptions 48 R 0x15 Read Write READI_DTA2 Data Trace Attributes Register 2 See Table 24 15 for bit descriptions 48 R 1 Not available on all revisions Refer...

Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...

Page 1145: ...eration of the chip clocks This appendix describes how the clock supplies and external components should be connected in a system These guidelines must be fulfilled to reduce switching noise which is...

Page 1146: ...ents See the circuit in Section 8 11 1 System Clock Control Register SCCR 2 Resistor R1 is currently not required Space should be left on the board to add it in the future if necessary 3 All 100 nF ca...

Page 1147: ...uF 1nF 10k 10 10 To From Sensors 100 nF 10 nF R23 Sensors 100 nF Analog ground plane ALTREF 100 nF VFLASH 1 10 ohms is recommended because IREF max is 250 A per QADC64 10 Ohm x 2 modules x 250 A 5 mV...

Page 1148: ...nce XTAL pad capacitance is CPAD 7 pF Table C 1 External Components Value For Different Crystals Q1 Component NDK CP32C 20 MHz KINSEKI CX 11F 20 MHz MURATA CCSTC 4 MHz Units CL 1 1 CL according to cry...

Page 1149: ...part Figure C 4 RC Filter Example Figure C 5 Bypass Capacitors Example Alternative C 2 2 PLL External Components VDDSYN and VSSSYN are the PLL dedicated power supplies These supplies must be used only...

Page 1150: ...s the PLL faster to gain lock but less stable Higher CXFC makes the PLL more stable but slower to gain lock Because each board layout and application is unique CXFC must be evaluated in a system The m...

Page 1151: ...SSSYN pin should be provided with an extremely low impedance path in the board All the filters for the supplies should be located as close as possible to the chip package It is recommended to design i...

Page 1152: ...it can sink without the regulated voltage rising out of range 1 Operating Conditions 40 C to 150 C all process variations 2 Supply Current includes SRAM array standby currents The boundary equations...

Page 1153: ...ess up to 8 Kbytes of memory at any one time It has 4 Kbytes of internal ROM located in banks 0 and 1 and 8 Kbytes of dual ported SRAM DPTRAM located in banks 0 1 2 and 3 As only one type of memory ca...

Page 1154: ...the microcontroller A customer may for example wish to use the ID function from bank 1 to verify the TPU3 microcode version but then use the MCPWM function from bank 0 As a customer will typically onl...

Page 1155: ...bank 0 will be selected by default To select the bank 0 entry table write 0b00 to the ETBANK field in TPUMCR2 Always initialize any write once register to ensure that an incorrect value is not accide...

Page 1156: ...bled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Cha...

Page 1157: ...be used as a discrete output pin QOM can generate pulse width modulated waveforms including waveforms with high times of 0 or 100 See Freescale TPU3 Progamming Note Queued Output Match TPU Function Q...

Page 1158: ...terrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM ADDRESS OFFSETS BITS 0 1 2 3 4 5 6...

Page 1159: ...ing full defininition of the profile In addition a slew rate parameter allows fine control of the motor s terminal running speed independent of the acceleration table The RCPU writes a desired positio...

Page 1160: ...30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt N...

Page 1161: ...el Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM ADDRESS OFFSETS BITS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30XX W...

Page 1162: ...nd continuous modes In continuous mode no pulses are lost between sample windows and the user can select whether to detect pulses on the rising or falling edge This function is intended for high speed...

Page 1163: ...d 0 1 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0...

Page 1164: ...r generation of even odd and no parity Baud rate is freely programmable and can be higher than 100 Kbaud Eight bidirectional UART channels running in excess of 9600 baud can be implemented on the TPU3...

Page 1165: ...nnel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM...

Page 1166: ...annel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM...

Page 1167: ...errupt request to notify the bus master times of the two most recent transitions remain in parameter RAM capture input continually or detect a specific number of transitions and end channel activity u...

Page 1168: ...30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt N...

Page 1169: ...t sensors The state sequence is implemented as a user configurable state machine providing a flexible approach with other general applications A RCPU offset parameter is provided to allow the RCPU to...

Page 1170: ...Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Inerrput Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status...

Page 1171: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor D 19 PRAM Address Offset Map Figure D 10 COMM Parameters...

Page 1172: ...function PARAMETER RAM ADDRESS OFFSETS BITS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30XX W 1 0 LENGTH STATE 0 PIN_CONFIG Param 8 0x30XX W 1 2 LENGTH STATE 1 PIN_CONFIG Param 9 0x30XX W 1 4 LENGTH STAT...

Page 1173: ...riority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status x Not Used 0x30YY20 PARAMETER RAM A...

Page 1174: ...QOM function Multiple PWMs generated by MCPWM have two types of high time alignment edge aligned and center aligned Edge aligned mode uses n 1 TPU3 channels for n PWMs and center aligned mode uses 2n...

Page 1175: ...0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel...

Page 1176: ...l Priority 00 Disabled 0x30YY18 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupt Enabled 0 cC...

Page 1177: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor D 25 See Table 19 24 for the PRAM Address Offset Map CONTROL BITS Figure D 13 MCPWM Parameters Slave Edge Aligned Mode...

Page 1178: ...iority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not As...

Page 1179: ...0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel Interru...

Page 1180: ...Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not...

Page 1181: ...C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel Inter...

Page 1182: ...r reaches zero PWM_IN This function analyses a PWM input signal by measuring a selectable number of periods It adds both periods as well as high time for the selected number of periods SPEED This func...

Page 1183: ...1 cChannel Priority 00 Disabled 0x30YY18 0x30YY1A 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not used 0x30YY1C 0x30YY1E 0 cChannel Interrupt Status x Not used 0x...

Page 1184: ...ty 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt...

Page 1185: ...ority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Ass...

Page 1186: ...led 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cChannel Interrupt Status 0 Ch...

Page 1187: ...g faster signals to be decoded Furthermore every counter update provides a time stamp that is useful for interpolating position and determining velocity at low speed or in instances that implement low...

Page 1188: ...riority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0x30YY0A 0 cChannel Interrupt Status x Not Used 0x30YY20 PARAMETER RAM...

Page 1189: ...d TCR1 11 Initialize 0 1 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0x30YY0A 0 cChannel Interrupt Status...

Page 1190: ...measurement and the latest complete accumulation over the programmed number of periods The pulse width high time portion of an input signal can be measured up to 24 bits and added to a previous measu...

Page 1191: ...s 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM ADDRESS OFFSETS BITS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30XXW0 START_LINK_ CHANNEL LINK_CHANNEL_ COUNT1 CHAN...

Page 1192: ...le Semiconductor D 14 ID TPU3 Function ID This is a simple function that returns the version of the TPU3 ROM on the current device Figure D 25 shows all of the host interface areas for the ID function...

Page 1193: ...0 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 C...

Page 1194: ...receiving a link from a channel OC references without RCPU interaction a specifiable period and calculates an offset that is equal to the period x the ratio where the ratio is a supplied parameter Thi...

Page 1195: ...Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Interrupt...

Page 1196: ...cy capability of the TPU3 To define the PWM the RCPU provides one parameter that indicates the period and another that indicates the high time Updates to one or both of these parameters can effect wav...

Page 1197: ...ty 10 Medium Priority 11 High Priority 0 cInterrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 cInterrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Int...

Page 1198: ...meter indicates the most recent state Bit 14 indicates the next most recent state and so on The programmer can update the parameter when a transition occurs when the RCPU makes a request or when a rat...

Page 1199: ...iority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel...

Page 1200: ...ction to maintain complex timing relationships between channels without RCPU intervention The SPWM output waveform duty cycle excludes 0 and 100 If it is not necessary for a PWM to maintain a time rel...

Page 1201: ...ority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Inter...

Page 1202: ...7 PARAMETER RAM MODE 2 ADDRESS OFFSETS BITS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x30XXW0 LASTRISE CHANNEL_CONTROL Param 0 0x30XXW2 NEXTRISE Param 1 0x30XXW4 HIGH_TIME Param 2 0x30XXW6 PERIOD Param...

Page 1203: ...state whether the pin is programmed as an input or output The function also receives links Upon receipt it will read the two TCRs into PRAM updating the pin state parameter and generating a maskable i...

Page 1204: ...10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A 1 Channel Interrupt Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1...

Page 1205: ...5 bit range of TCR1 counts 3 Selection of MSB or LSB first shift direction 4 Variable transfer size from 1 to 16 bits 5 Programmable clock polarity When a transfer of data is complete the SIOP functio...

Page 1206: ...Functions MPC561 MPC563 Reference Manual Rev 1 2 D 54 Freescale Semiconductor NOTE Only the clock channel requires any programming The data in and data out channels are entirely under TPU3 microcode...

Page 1207: ...lock Channel and Start Transfer 0 1 Channel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Disabled 0x30YY0A...

Page 1208: ...other system conditions See the notes in Section D 20 1 6 SIOP_DATA for information on the use and performance of the SIOP function D 20 1 4 BIT_COUNT The TPU3 uses this parameter to count down the nu...

Page 1209: ...ts 3 Writing CHAN_CONTROL in the clock channel parameter RAM 4 Writing HALF_PERIOD BIT_D and XFER_SIZE in the clock channel parameter RAM to determine the speed shift direction and size of the transfe...

Page 1210: ...byte This is true for all data sizes except 16 bits in which case the full SIOP_DATA register is used for both data output and input D 20 3 3 Data Timing In the example given in Figure D 33 the data...

Page 1211: ...Td and ensure that the baud rate is chosen such that HALF_PERIOD Td is not less that the minimum setup time of the receiving device A transmitting device must also hold data valid for a minimum time...

Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...

Page 1213: ...basic delay of an external bus to a U bus is four clocks external master case All IMB accesses are assumed to be 16 bit accesses only If 32 bit accesses are used then each such IMB access is split int...

Page 1214: ...10 11 12 13 Load Store Ebus L U E 61 E U L Load Store IMB 16 bits L U IMB 6 IMB U L Instruction Fetch cmf new page 3 consecutive accesses C U 2 U2 C U 1 U C U 1 U Instruction Fetch DECRAM Decompressi...

Page 1215: ...e clocks from external address valid until external data valid In the case of zero wait states N 2 2 Core instruction fetch data bus is usually the U bus 3 8 clocks are dedicated for external accesses...

Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...

Page 1217: ...1 VDDSYN 0 3 3 0 V 7 N A 8 QADC Supply Voltage6 VDDA 0 3 5 6 V 9 5 V Supply Voltage VDDH 0 3 5 6 V 10 DC Input Voltages7 8 VIN VSS 0 3 5 69 V 11 Reference VRH with reference to VRL VRH 0 3 5 6 V 12 Re...

Page 1218: ...t be 1 75mA 6 VDDA 5 0 V 5 7 All 2 6 V input only pins are 5 V tolerant 8 Note that long term reliability may be compromised if 2 6 V output drivers drive a node which has been previously pulled to 3...

Page 1219: ...s are the mean 3 standard deviations of characterized data C W BGA Package Thermal Resistance Junction to Ambient Four layer 2s2p board natural convection R JMA 29 43 4 5 4 Junction temperature is a f...

Page 1220: ...ce the air flow can be changed around the device add a heat sink change the mounting arrangement on printed circuit board or change the thermal dissipation on the printed circuit board surrounding the...

Page 1221: ...op of package C JT thermal characterization parameter PD power dissipation in package The thermal characterization parameter is measured per JESD51 2 specification published by JEDEC using a 40 gauge...

Page 1222: ...1500 C 100 pF ESD for Machine Model MM 200 V MM Circuit Description R1 0 C 200 pF Number of pulses per pin2 Positive pulses MM Negative pulses MM Positive pulses HBM Negative pulses HBM 2 A device wil...

Page 1223: ...e GPIO VIH2 6M VIH5M 2 0 0 7 VDDH VDDH 0 3 VDDH 0 3 V V 6 2 6 V Input Low Voltage Except EXTCLK VIL2 6 VSS 0 3 0 8 V 7 2 6 V Input Low Voltage EXTCLK VIL2 6C VSS 0 3 0 4 V 8 5 V Input Low Voltage VIL5...

Page 1224: ...pins GPIO MUXed with Addr Data 2 6 V Output Low Voltage IOL 3 2mA 5 V Output Low Voltage IOL 2mA VOL2 6M VOL5M 0 5 0 45 V 25 Output Low Current VOL2 6 0 4 V IOL2 6 2 0 mA 27 CLKOUT Load Capacitance S...

Page 1225: ...10 A 38 Low Power Current QVDDL NVDDI VDD 56 MHz DOZE Active PLL and Active Clocks SLEEP Active PLL with Clocks off DEEP SLEEP PLL and Clocks off IDDDZ IDDSLP IDDDPSLP 110 15 8 mA mA mA 39 NVDDL QVDDL...

Page 1226: ...s can withstand up to 3 6 volts for a cumulative time of 24 hours over the lifetime of the device 4 This characteristic is for 5 V output and 5 V input pins 5 0 3V VDDA or VDDH whichever is greater 6...

Page 1227: ...is limit can cause disruption of normal operation 26 Current refers to two QADC64 modules operating simultaneously 27 Below disruptive current conditions the channel being stressed has conversion valu...

Page 1228: ...tes per word or 131 072 words no software overhead 15 20 s Table F 7 CENSOR Cell Program and Erase Characteristics Symbol Meaning Value Units Minimum Typical1 1 Typical set and clear times assume nomi...

Page 1229: ...s F 8 1 Power Up Down Option A The Option A power up sequence excluding VDDKA is 1 VDDH VDDL 3 1 V VDDH cannot lead VDDL by more than 3 1 V 2 VDDH VDDL 0 5 V VDDH cannot lag VDDL by more than 0 5 V Th...

Page 1230: ...the same instant or before both the high voltage and low voltage supplies are powered up Figure F 1 Option A Power Up Sequence Without Keep Alive Supply Figure F 2 Option A Power Up Sequence With Keep...

Page 1231: ...y be implemented if 2 6 V compliant pins and dual 2 6 V 5 V compliant pins are NOT connected to the 5 V supply with a pull up resistor or driven by 5 V logic during power up down VDDH VDDL 3 1 V Max R...

Page 1232: ...start to conduct current Figure F 5 illustrates the power up sequence if no keep alive supply is required Figure F 6 illustrates the power up sequence if a keep alive supply is required The keep alive...

Page 1233: ...ply F 9 Issues Regarding Power Sequence F 9 1 Application of PORESET or HRESET When VDDH is rising and VDDL is at 0 0 V as VDDH reaches 1 6 V all 5 V drivers are tristated Before VDDH reaches 1 6V all...

Page 1234: ...r non coherent store multiple either of the following solutions is recommended Assert HRESET at least 0 5 s prior to when PORESET is asserted Assert IRQ0 non maskable interrupt at least 0 5 s prior to...

Page 1235: ...VIH VIL VIL VIH VIH VIL VIL VIH A B C D C D A Maximum Output Delay Specification B Minimum Output Hold Time C Minimum input Setup Time Specification D Minimum input Hold Time Specification 5 V OUTPUT...

Page 1236: ...k pulse width low 12 5 2 12 5 2 8 93 2 8 93 2 ns 3 Clock pulse width high 12 5 2 12 5 2 8 93 2 8 93 2 ns 4 CLKOUT rise time ABUS DBUS rise time 3 5 3 0 3 5 3 0 ns 5 CLKOUT fall time ABUS DBUS fall tim...

Page 1237: ...8c Slave Mode CLKOUT to Signal Valid D 0 31 14 11 ns 8d CLKOUT to Data Pre discharge time 16 16 ns 8e CLKOUT to Data Pre discharge start 3 3 ns 9 CLKOUT to High Z ADDR 8 31 RD WR BURST D 0 31 TSIZ 0...

Page 1238: ...S BB High Z 6 25 20 4 5 16 ns 12a CLKOUT to TA BI High Z when driven by the Memory Controller 15 15 ns 13 CLKOUT to TEA assertion 8 5 8 5 ns 14 CLKOUT to TEA High Z 15 15 ns 15 Input Valid to CLKOUT S...

Page 1239: ...10 TRLX 0 or 1 8 6 ns 19b CLKOUT Falling Edge to CS asserted GPCM ACS 11 TRLX 0 or 1 6 25 14 5 5 10 5 ns 19c CLKOUT Falling Edge to CS asserted GPCM ACS 11 TRLX 0 EBDF 1 6 25 17 6 69 12 69 ns 20 CLKO...

Page 1240: ...g Edge to CS negated GPCM write access TRLX 0 or 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 6 25 14 5 5 10 5 ns 25c CLKOUT Falling Edge to WE 0 3 BE 0 3 negated GPCM write access TRLX 0 CSNT 1 EBDF 1 6 25 17 5...

Page 1241: ...0 28 20 ns 26f WE 0 3 BE 0 3 negated to D 0 31 HighZ GPCM write access TRLX 0 CSNT 1 EBDF 1 5 3 75 ns 26g CS negated to D 0 31 High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 5 3 75 ns...

Page 1242: ...3 negated to ADDR 8 31 invalid GPCM write access TRLX 0 CSNT 1 CS negated to ADDR 8 31 Invalid GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 4 3 ns 27d WE 0 3 BE 0 3 negated to ADDR 8 31 Inval...

Page 1243: ...when the MPC561 MPC563 is selected to work with internal bus arbiter 3 The setup times required for TA TEA and BI are relevant only when they are supplied by the external device and not the memory co...

Page 1244: ...ical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 28 Freescale Semiconductor Figure F 11 Synchronous Output Signals Timing 8 8a 7b 9 9 7a 7 8b CLKOUT OUTPUT SIGNALS OUTPUT SIGNALS OUTPUT S...

Page 1245: ...stics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 29 Figure F 12 Predischarge Timing 8e CLKOUT DATA 8d 0V 3 1V 5 25V 2 6V sp8e clkout to predischarge drivers enabled sp8d clkout t...

Page 1246: ...Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 30 Freescale Semiconductor Figure F 13 Synchronous Active Pull Up And Open Drain Outputs Signals Timing 10 12 11 10a 12a 11a 13 14 CLKOUT TS BB...

Page 1247: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 31 Figure F 14 Synchronous Input Signals Timing 15 16 15a 16a 15b 16 CLKOUT TA BI TEA KR RETRY CR BB BG BR...

Page 1248: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 32 Freescale Semiconductor Figure F 15 Input Data Timing In Normal Case 15a 16 17 18 DATA 0 31 TA CLKOUT...

Page 1249: ...teristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 33 Figure F 16 External Bus Read Timing GPCM Controlled ACS 00 8 10 19 22 11 20 23 17 18 25 CLKOUT TS ADDR 8 31 CSx OE WE 0 3...

Page 1250: ...racteristics MPC561 MPC563 Reference Manual Rev 1 2 F 34 Freescale Semiconductor Figure F 17 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 8 10 19a 22 11 20 23 17 18 21 CLKOUT TS ADDR 8 31 CS...

Page 1251: ...teristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 35 Figure F 18 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 19c 19b 8 10 22 11 20 23 17 18 21a CLKOUT TS ADDR 8 31...

Page 1252: ...Rev 1 2 F 36 Freescale Semiconductor Figure F 19 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 Figure F 20 Address Show Cycle Bus Timing 8 19a 11 20 23 17 18 24 24a 19b 19c 10 CLKOUT T...

Page 1253: ...trical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 37 Figure F 21 Address and Data Show Cycle Bus Timing 8 10 11 9 8 27 DATA 0 31 CLKOUT TS ADDR 8 31 CSx WE 0 3 BE...

Page 1254: ...s MPC561 MPC563 Reference Manual Rev 1 2 F 38 Freescale Semiconductor Figure F 22 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 8 10 19 22 11 20 25 9 23 8 26 26b 27 DATA 0 31 OE WE 0 3 BE 0...

Page 1255: ...563 Reference Manual Rev 1 2 Freescale Semiconductor F 39 Figure F 23 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 1 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c D 0 31 OE...

Page 1256: ...Reference Manual Rev 1 2 F 40 Freescale Semiconductor Figure F 24 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c CLKOUT TS...

Page 1257: ...PC563 Reference Manual Rev 1 2 Freescale Semiconductor F 41 Figure F 25 External Master Read From Internal Registers Timing 29 28 30 10a 12a 11a 13 14 9 8 10b 11b CLKOUT TS ADDR 8 31 TSIZ 0 1 RD WR BU...

Page 1258: ...MPC563 Reference Manual Rev 1 2 F 42 Freescale Semiconductor Figure F 26 External Master Write To Internal Registers Timing 29 28 30 10a 12a 11a 13 14 28a 18 10b 11b CLKOUT TS ADDR 8 31 TSIZ 0 1 RD W...

Page 1259: ...ulse width Low TC TC ns 34 IRQx Pulse width High Between Level IRQ TC TC ns 35 IRQx Edge to Edge time 4 TC 4 TC ns Table F 12 Debug Port Timing Note TA TL to TH Characteristic 40 MHz 56 MHz Unit Min M...

Page 1260: ...l Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 44 Freescale Semiconductor Figure F 28 Debug Port Clock Input Timing Figure F 29 Debug Port Timings 36 36 37 37 38 38 DSCK 40 42 41 39 DSCK D...

Page 1261: ...pF load unless noted otherwise Number Characteristic Min Max Unit 1 MCKO Cycle Time Tco 17 9 ns 2 MCKO Duty Cycle 40 60 3 Output Rise and Fall Times 0 3 ns 4 MCKO low to MDO Data Valid 1 79 3 58 ns 5...

Page 1262: ...on When RSTI is asserted EVTI is used to enable or disable the auxiliary port Because MCKO probably is not active at this point the timing must be based on the system clock Since the system clock is n...

Page 1263: ...timing will comply with the 130 A mode select current outlined in XrefBlue Table F 5 on page F 7 The system requires two clocks of hold time on RSTCONF TEXP after negation of HRESET The simplest way...

Page 1264: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 48 Freescale Semiconductor Figure F 34 Reset Timing Configuration from Data Bus 46 48 49 45 47 49a HRESET RSTCONF DATA 0 31 IN...

Page 1265: ...l Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 49 Figure F 35 Reset Timing Data Bus Weak Drive During Configuration 50 51 52 43 55a CLKOUT HRESET RSTCONF DATA 0 31...

Page 1266: ...d at VDD 2 50 ns 58 TCK Rise and Fall Times 0 10 ns 59 TMS TDI Data Setup Time 5 ns 60 TMS TDI Data Hold Time 25 ns 61 TCK Low to TDO Data Valid 20 ns 62 TCK Low to TDO Data Invalid 0 ns 63 TCK Low to...

Page 1267: ...PC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 51 Figure F 37 JTAG Test Clock Input Timing 1 JTAG timing TCK is only tested at 10 MHz TCK is the operating clock of the MPC561 MPC563 i...

Page 1268: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 52 Freescale Semiconductor Figure F 38 JTAG Test Access Port Timing Diagram 60 62 59 61 63 TCK TMS TDI TDO...

Page 1269: ...ectrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 53 Figure F 39 Boundary Scan JTAG Timing Diagram 66 67 68 69 70 OUTPUT SIGNALS TCK OUTPUT SIGNALS OUTPUT SIGNA...

Page 1270: ...Hz3 2 clock input sample time 4 Accuracy tested and guaranteed at VRH VRL 5 0 V 0 25 V 5 This parameter is periodically sampled rather than 100 tested 6 Absolute error includes 1 2 count 2 5 mV of inh...

Page 1271: ...the larger of the calculated values The diode drop voltage is a function of current and varies approximately 0 4 to 0 8 V over temperature 15 This parameter is periodically sampled rather 100 tested 1...

Page 1272: ...C SCK 2 ns ns 112 Clock SCK High or Low Time Master Slave3 tSW 2 TC 60 2 TC n 255 TC ns ns 113 Sequential Transfer Delay Master Slave Does Not Require Deselect tTD 17 TC 13 TC 8192 TC ns ns 114 Data S...

Page 1273: ...is tested to the 5 V levels outlined in XrefBlue Table F 5 on page F 7 2 TC is defined to be the clock period 3 For high time n External SCK rise time for low time n External SCK fall time Table F 18...

Page 1274: ...OUT MSB IN MSB OUT DATA LSB OUT PORT DATA PCS 0 3 OUTPUT PD MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 111 110 113 121 120 112 109 114 115 111 120 121 119 118 121 120 OUTPUT MSB MSB MSB OUT...

Page 1275: ...OUT PD MSB OUT MSB IN MSB OUT MSB IN DATA LSB IN SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT MISO OUTPUT MOSI INPUT 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 DATA SLAVE L...

Page 1276: ...QGPIO 0 3 MPIO32B 11 12 rise time Input t RI 1 ms Output PDMCR SLRC0 0 50 pF Load1 t RO 50 ns Output PDMCR SLRC0 1 50 pF Load t RO 21 ns 122c SGPIOC 0 5 rise time 2 Input t RI 1 s Output SCCR COM 0b11...

Page 1277: ...hese are 2 6 V GPIO pins Table F 20 TPU3 Timing Note TA TL to TH Num Rating Symbol Min Max Unit 124 Slew Rate of TPU Output Channel Valid1 2 SLRC0 of PDMCR 0 50 pF to 200 pF load SLRC0 of PDMCR 1 50 p...

Page 1278: ...PDMCR 0 50 pF SLRC1 bit of PDMCR 1 tRI tRO 1 50 100 25 s ns ns ns 130 Fall Time Input Output 50 pF load SLRC1 bit of PDMCR 0 200 pF load SLRC1 bit of PDMCR 0 50 pF SLRC1 bit of PDMCR 1 tFI tFO 1 50 10...

Page 1279: ...ut Output 2 6V PPM pads PDMCR2 PPMV 0 5V PPM pads PDMCR2 PPMV 1 tFI tFO 1 7 15 s ns ns 1 All AC timing is tested to the 2 6 V levels outlined in XrefBlue Table F 5 on page F 7 2 Although the PPM permi...

Page 1280: ...Unit MCPSM enable to VS_PCLK pulse1 1 The MCPSM clock prescaler value MCPSMSCR_PSL 3 0 should be written to the MCPSMSCR MCPSM Status Control Register before rewriting the MCPSMSCR to set the enable...

Page 1281: ...t resolution depends on MPWMSM and MCPSM prescaler settings 2 Maximum resolution is obtained by setting CPSMPSL 3 0 0x2 and MPWMSCR_CP 7 0 0xFF 3 Excluding the case where the output is always 0 4 With...

Page 1282: ...ge Timing Diagram Figure F 50 MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram Figure F 51 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram fSYS bit PREN MIOB VS_PCLK...

Page 1283: ...pin to PINL delay tPINL 1 2 Counter bus resolution tCBR 1 1 Minimum output resolution depends on MMCSM and MCPSM prescaler settings 2 2 2 Maximum resolution is obtained by setting CPSMPSL 3 0 0x2 and...

Page 1284: ...ement Timing Diagram Figure F 54 MMCSM Load Pin To Counter Bus Reload Timing Diagram Figure F 55 MMCSM Counter Bus Reload To Interrupt Flag Setting Timing Diagram fSYS MMCSM clock pin tPCCB Counter bu...

Page 1285: ...when the counter bus is changing then the capture is delayed one cycle In situations where the counter bus is stable when the input capture occurs the tPCAP has a maximum delay of two cycles the one c...

Page 1286: ...OTE fSYS is the internal system clock for the IMB3 bus Figure F 58 MDASM Input Pin To Counter Bus Capture Timing Diagram Figure F 59 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram fSYS MDAI in...

Page 1287: ...ter Bus to MDASM Interrupt Flag Setting Timing Diagram F 21 MPIOSM Timing Characteristics Table F 27 MPIOSM Timing Characteristics Note All delays are in system clock periods Characteristic Symbol Min...

Page 1288: ...ut pin to MPIOSM_DR delay tPDR 0 1 Output mode Output pulse width 2 tPULW 2 1 The minimum input pin period pin low and pin high times depend on the rate at which the MPIOSM_DR register is polled 2 The...

Page 1289: ...pioa8 AF9 addr_sgpioa9 AF8 addr_sgpioa10 AC6 addr_sgpioa11 Y4 addr_sgpioa12 Y3 addr_sgpioa13 AD7 addr_sgpioa14 AE7 addr_sgpioa15 AF7 addr_sgpioa16 AD8 addr_sgpioa17 AE8 addr_sgpioa18 AC7 addr_sgpioa19...

Page 1290: ...AC17 data_sgpiod12 AC18 data_sgpiod13 AD18 data_sgpiod14 AC20 data_sgpiod15 AD19 data_sgpiod16 AD20 data_sgpiod17 AE20 data_sgpiod18 AF20 data_sgpiod19 AE19 data_sgpiod20 AF19 data_sgpiod21 AE18 data_...

Page 1291: ...sel R26 TSIZ 0 1 tsiz0 V4 tsiz1 W1 RD WR rd_wr _b V1 BURST burst Y1 BDIP bdip_b W4 TS ts_b W2 TA ta_b W3 TEA tea_b V3 RSTCONF TEXP rstconf_b_texp Y25 OE oe_b V2 BI STS bi_b_sts_b Y2 CS 0 3 cs0_b U1 cs...

Page 1292: ...L xtal AD26 EXTAL extal AC26 XFC xfc AA26 CLKOUT clkout U23 EXTCLK extclk V24 ENGCLK BUCLK engclk_buclk V26 QSMCM PCS0 SS QGPIO0 pcs0_ss_b_qgpio0 N25 PCS 1 3 QGPIO 1 3 pcs1_qgpio1 N24 pcs2_qgpio2 N23...

Page 1293: ...b0_mdo1 L23 VF1 MPIO32B1 MCKO vf1_mpio32b1_mcko L24 VF2 MPIO32B2 MSEI vf2_mpio32b2_msei_b M24 VFLS0 MPIO32B3 MSEO vfls0_mpio32b3_mseo_b M25 VFLS1 MPIO32B4 vfls1_mpio32b4 M26 MPIO32B5 MDO5 mpio32b5_mdo...

Page 1294: ...x0 L25 TPU_A TPU_B A_TPUCH 0 15 a_tpuch0 F3 a_tpuch1 C5 a_tpuch2 B5 a_tpuch3 A5 a_tpuch4 C6 a_tpuch5 D6 a_tpuch6 B6 a_tpuch7 A6 a_tpuch8 C7 a_tpuch9 D7 a_tpuch10 B7 a_tpuch11 A7 a_tpuch12 C8 a_tpuch13...

Page 1295: ...a_t2clk_pcs5 F2 B_T2CLK PCS4 b_t2clk_pcs4 F1 QADC64E_A QADC64E_B ETRIG 1 2 PCS 6 7 etrig1_pcs6 B20 etrig2_pcs7 A20 A_AN0 ANw PQB0 a_an0_anw_pqb0 C11 A_AN1 ANx PQB1 a_an1_anx_pqb1 D11 A_AN2 ANy PQB2 a_...

Page 1296: ...4 7 b_an48_pqb4 A16 b_an49_pqb5 B16 b_an50_pqb6 C16 b_an51_pqb7 D16 B_AN 52 54 MA 0 2 PQA 0 2 b_an52_ma0_pqa0 A17 b_an53_ma1_pqa1 B17 b_an54_ma2_pqa2 C17 B_AN 55 59 PQA 3 7 b_an55_pqa3 D17 b_an56_pqa4...

Page 1297: ...ctor F 81 Global Power Supplies NVDDL nvddl AC10 AC15 AC19 AC4 AD3 AE2 AF1 C9 D9 Y23 VDD vdd A1 A25 AC22 AD23 AE24 AF25 B2 B24 C23 C3 D22 D4 V23 VDDH vddh AF21 AF5 C19 C22 D19 E1 F23 T25 Table F 28 MP...

Page 1298: ...C24 C26 C4 D1 D2 D23 D25 D26 D3 D5 E2 E24 E25 E26 E3 E4 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16...

Page 1299: ...balls in the perimeter rows and 36 ground balls in the center island for a total of 388 balls The case outline drawing is 1164 01 as shown in Figure F 64 ALTREF altref B10 VDDA vdda D10 VSSA vssa A9...

Page 1300: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 F 84 Freescale Semiconductor 1 NOTE Top Down View Figure F 64 MPC561 MPC563 Package Footprint 1 of 2...

Page 1301: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor F 85 Figure F 65 MPC561 MPC563 Package Footprint 2 of 2...

Page 1302: ...1 SGPIOC6_ FRZ_PTR_ B VSS VSS VSS VSS VSS VSS PCS2_QGPI O2 PCS1_QGPIO1 PCS0_SS_B_ QGPIO0 A_CNRX0 N P IRQ4_B_AT 2_SGPIOC4 IRQ2_B_C R_B_SGPI OC2_MDO 5_MTS IRQ0_B_S GPIOC0_ MDO4 IRQ1_B_R SV_B_SG PIOC1 VS...

Page 1303: ..._A NW_PQB 0 A_AN48_P QB4 A_AN52_ MA0_PQ A0 A_AN59_P QA7 D VSS VSS VSS VDD VSS A_TPUCH5 A_TPUCH 9 A_TPUCH13 NVDDL VDDA A_AN1_A NX_PQB1 A_AN49_P QB5 A_AN53_ MA1_PQ A1 A_AN57_P QA5 E VDDH VSS VSS VSS F B...

Page 1304: ...B CS3_B V RD_WR_B OE_B TEA_B TSIZ0 W TSIZ1 TS_B TA_B BDIP_B Y BURST_B BI_B_STS_ B ADDR_SG PIOA12 ADDR_SG PIOA11 AA VSS VSS VSS QVDDL AB VSS VSS QVDDL VSS AC VSS QVDDL VSS NVDDL VSS ADDR_SGP IOA10 ADDR...

Page 1305: ...SS VDD VSS QVDDL B A_AN59_P QA7 B_AN2_AN Y_PQB2 B_AN50_ PQB6 B_AN54_M A2_PQA2 B_AN58_P QA6 VDDH MDA11 MDA15 VDDH VDD VSS QVDDL VSS C A_AN57_P QA5 B_AN3_AN Z_PQB3 B_AN51_ PQB7 B_AN55_P QA3 B_AN59_P QA7...

Page 1306: ..._B SRESET_B PORESET_B _TRST_B KAPWR W NVDDL IRQ7_B_MODC K3 RSTCONF_B _TEXP VDDSYN Y VSS VSS VSS XFC AA QVDDL VSS VSS VSSSYN AB DATA_SG PIOD7 NVDDL DATA_SG PIOD9 DATA_SGP IOD11 DATA_SG PIOD12 NVDDL DAT...

Page 1307: ...tages higher than 3 1 V on the data bus In a dual controller application with the MPC563 as master and MPC561 as slave revision D of MPC561 silicon must be used Table G 1 Absolute Maximum Ratings VSS...

Page 1308: ...which has been previously pulled to 3 1 V by an external component HRESET and SRESET are fully 5 V compatible 9 6 35 V on 5 V only pins all QADC all TPU all QSMCM and the following MIOS pins MDA 11 1...

Page 1309: ...ng a 1 0 mm ball pitch Freescale case outline 1164 01 See Figure G 63 and Figure G 64 G 3 EMI Characteristics G 3 1 Reference Documents The document referenced for the EMC testing of MPC561 MPC563 is...

Page 1310: ...JT 7 03 7 C W BGA Package Thermal Resistance Junction to Package Top Natural Convection JT 1 68 C W 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounti...

Page 1311: ...ture in the environment can be made using the following equation TJ TB R JB x PD where TB board temperature C R JB package junction to board resistance C W PD power dissipation in package If the board...

Page 1312: ...tion of a 272 PBGA Within an Automotive Engine Controller Module Proceedings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resista...

Page 1313: ...V 6 2 6 V Input Low Voltage Except EXTCLK VIL2 6 VSS 0 3 0 8 V 7 2 6 V Input Low Voltage EXTCLK VIL2 6C VSS 0 3 0 4 V 8 5 V Input Low Voltage VIL5 VSS 0 3 0 48 VDDH V 9 5 V Input Low Voltage QADC PQA...

Page 1314: ...Low Voltage IOL 2mA VOL2 6M VOL5M 0 5 0 45 V 25 Output Low Current VOL2 6 0 4 V IOL2 6 2 0 mA 27 CLKOUT Load Capacitance SCCR COM CQDS COM 0 1 0b01 CQDS 0b1 COM 0 1 0b01 CQDS 0b0 COM 0 1 0b00 CQDS 0bx...

Page 1315: ...SYN VDD 0 2 V VDD 0 2 V12 V 46 N A 47 VSS Differential Voltage VSS VSSA 100 100 mV 48 QADC64 Reference Voltage Low13 VRL VSSA VSSA 0 1 V 49 QADC64 Reference Voltage High13 VRH 3 0 VDDA V 50 QADC64 VRE...

Page 1316: ...connect this pin to 2 6V or 3 3V however it can be connected to 0V or 5V without damage to the device 15 A resistor must be placed in series with the IRAMSTBY power supply Refer to Appendix C Clock a...

Page 1317: ...aracteristics Symbol Meaning Value Units Minimum Typical1 1 Typical program and erase times assume nominal supply values and 25 C Maximum TERASE Block Erase Time2 2 Erase time specification does not i...

Page 1318: ...mum data retention at an average of 125 C junction temperature Min 15 years3 Min 10 years3 3 Maximum total time 150 C junction temperature 1 year Table G 9 Power Supply Pin Groups Symbol Types of Powe...

Page 1319: ...1 Power Up Down Option A The Option A power up sequence excluding VDDKA is 1 VDDH VDDL 3 1 V VDDH cannot lead VDDL by more than 3 1 V 2 VDDH VDDL 0 5 V VDDH cannot lag VDDL by more than 0 5 V The fir...

Page 1320: ...L by more than 0 5 V Figure G 3 illustrates the power down sequence if no keep alive supply is required Figure G 3 Option A Power Down Sequence Without Keep Alive Supply VDDH VDDL 3 1 V lead 0 5 V lag...

Page 1321: ...y group can be fully powered up prior to power up of the VDDL supply group with no adverse affects to the device The requirement that VDDH cannot lag VDDL by more than 0 5 V is due to ESD diodes in th...

Page 1322: ...prior to power down of the VDDH supply group with no adverse affects to the device For power down the low voltage supply should come down before the high voltage supply although with varying loads th...

Page 1323: ...the 5 V drivers can come out of tristate when VDDL reaches 1 1V and the 2 6 V drivers can start driving when VDDL reaches 0 5 V For these reasons the PORESET or HRESET signal must be asserted during p...

Page 1324: ...sserted Assert IRQ0 non maskable interrupt at least 0 5 s prior to when PORESET is asserted The service routine for IRQ0 should not perform any writes to keep alive RAM The amount of delay that should...

Page 1325: ...VOH VIH VIL VIL VIH VIH VIL VIL VIH A B C D C D A Maximum Output Delay Specification B Minimum Output Hold Time C Minimum input Setup Time Specification D Minimum input Hold Time Specification 5 V OU...

Page 1326: ...lse width low 7 575 2 7 575 2 ns 3 Clock pulse width high 7 575 2 7 575 2 ns 4 CLKOUT rise time ABUS DBUS rise time 3 5 3 0 ns 5 CLKOUT fall time ABUS DBUS fall time 3 5 3 0 ns 6 N A 7 CLKOUT to Signa...

Page 1327: ...RST D 0 31 TSIZ 0 1 RSV AT 0 3 PTR RETRY 5 95 9 8 ns 10 CLKOUT to TS BB assertion 3 33 7 9 ns 10a CLKOUT to TA BI assertion when driven by the Memory Controller 7 85 ns 10b CLKOUT to RETRY assertion w...

Page 1328: ...OUT to Signal Invalid Hold Time TA TEA BI BB BG BR1 2 1 ns 16a CLKOUT to Signal Invalid Hold Time RETRY KR CR 1 ns 17 Signal Valid to CLKOUT Rising Edge Setup Time D 0 31 3 4 ns 17b Signal Valid to CL...

Page 1329: ...ns 25 CLKOUT Rising Edge to WE 0 3 BE 0 3 negated GPCM write access CSNT 0 4 75 ns 25a CLKOUT Falling Edge to WE 0 3 BE 0 3 negated GPCM write access TRLX 0 or 1 CSNT 1 EBDF 0 4 5 9 5 ns 25b CLKOUT Fa...

Page 1330: ...ns 26i CS negated to D 0 31 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 14 65 ns 27 CS WE 0 3 BE 0 3 negated to ADDR 8 31 invalid GPCM write access5 1 2 ns 27a WE 0 3 BE 0 3 negated...

Page 1331: ...he timing for BG output is relevant when the MPC561 MPC563 is selected to work with internal bus arbiter 2 The setup times required for TA TEA and BI are relevant only when they are supplied by the ex...

Page 1332: ...ctrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 26 Freescale Semiconductor Figure G 11 Synchronous Output Signals Timing 8 8a 7b 9 9 7a 7 8b CLKOUT OUTPUT SIGNALS OUTPUT SIGNALS OUTPU...

Page 1333: ...cal Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 27 Figure G 12 Synchronous Active Pull Up And Open Drain Outputs Signals Timing 10 12 11 10a 12a 11a 13 14 CLKOUT T...

Page 1334: ...MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 28 Freescale Semiconductor Figure G 13 Synchronous Input Signals Timing 15 16 15a 16a 15b 16 CLKOUT TA BI TEA KR RETRY CR BB BG...

Page 1335: ...66 MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 29 Figure G 14 Input Data Timing In Normal Case 15a 16 17 18 DATA 0 31 TA CLKOUT...

Page 1336: ...racteristics MPC561 MPC563 Reference Manual Rev 1 2 G 30 Freescale Semiconductor Figure G 15 External Bus Read Timing GPCM Controlled ACS 00 8 10 19 22 11 20 23 17 18 25 CLKOUT TS ADDR 8 31 CSx OE WE...

Page 1337: ...Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 31 Figure G 16 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 8 10 19a 22 11 20 23 17 18 21 CLKOUT TS ADDR 8 31...

Page 1338: ...aracteristics MPC561 MPC563 Reference Manual Rev 1 2 G 32 Freescale Semiconductor Figure G 17 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 19c 19b 8 10 22 11 20 23 17 18 21a CLKOUT TS ADDR 8...

Page 1339: ...ristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 33 Figure G 18 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 8 19a 11 20 23 17 18 24 24a 19b 19c 10 CLKOUT TS A...

Page 1340: ...66 MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 34 Freescale Semiconductor Figure G 19 Address Show Cycle Bus Timing 11 10 8 9 CLKOUT TS ADDR 8 31...

Page 1341: ...lectrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 35 Figure G 20 Address and Data Show Cycle Bus Timing 8 10 11 9 8 27 DATA 0 31 CLKOUT TS ADDR 8 31 CSx WE 0 3...

Page 1342: ...tics MPC561 MPC563 Reference Manual Rev 1 2 G 36 Freescale Semiconductor Figure G 21 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 8 10 19 22 11 20 25 9 23 8 26 26b 27 DATA 0 31 OE WE 0 3 BE...

Page 1343: ...MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 37 Figure G 22 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 1 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c D 0 31...

Page 1344: ...563 Reference Manual Rev 1 2 G 38 Freescale Semiconductor Figure G 23 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c CLKOUT...

Page 1345: ...61 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 39 Figure G 24 External Master Read From Internal Registers Timing 29 28 30 10a 12a 11a 13 14 9 8 10b 11b CLKOUT TS ADDR 8 31 TSIZ 0 1 RD W...

Page 1346: ...te To Internal Registers Timing Table G 11 Interrupt Timing Note TA TL to TH Characteristic 66 MHz Unit Min Max 33 IRQx Pulse width Low TC ns 34 IRQx Pulse width High Between Level IRQ TC ns 35 IRQx E...

Page 1347: ...G 11 1 Debug Port Timing Table G 12 Debug Port Timing Note TA TL to TH Characteristic 66 MHz Unit Min Max 36 DSCK Cycle Time 30 30 ns 37 DSCK Clock Pulse Width 15 15 ns 38 DSCK Rise and Fall Times 0...

Page 1348: ...rical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 42 Freescale Semiconductor Figure G 27 Debug Port Clock Input Timing Figure G 28 Debug Port Timings 36 36 37 37 38 38 DSCK 40 42 41 39 DS...

Page 1349: ...m clock is not realized on the connector its value must be known by the tool Table G 13 READI AC Electrical Characteristics Note VDD 2 6 V 0 1 V VDDH 5 0 V 0 25 V TA TL to TH 50 pF load unless noted o...

Page 1350: ...edge Setup Time 231 ns 47 Configuration Data to RSTCONF rising edge set up time 231 ns 48 Configuration Data hold time after RSTCONF negation 0 ns 49 Configuration Data hold time after HRESET negatio...

Page 1351: ...age G 7 The system requires two clocks of hold time on RSTCONF TEXP after negation of HRESET The simplest way to insure meeting this requirement in systems that require the use of the TEXP function is...

Page 1352: ...rical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 46 Freescale Semiconductor Figure G 34 Reset Timing Data Bus Weak Drive During Configuration 50 51 52 43 55a CLKOUT HRESET RSTCONF DATA 0...

Page 1353: ...ured at VDD 2 50 ns 58 TCK Rise and Fall Times 0 10 ns 59 TMS TDI Data Setup Time 5 ns 60 TMS TDI Data Hold Time 25 ns 61 TCK Low to TDO Data Valid 20 ns 62 TCK Low to TDO Data Invalid 0 ns 63 TCK Low...

Page 1354: ...2 G 48 Freescale Semiconductor Figure G 36 JTAG Test Clock Input Timing Figure G 37 JTAG Test Access Port Timing Diagram 1 JTAG timing TCK is only tested at 10 MHz TCK is the operating clock of the MP...

Page 1355: ...Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 49 Figure G 38 Boundary Scan JTAG Timing Diagram 66 67 68 69 70 OUTPUT SIGNALS TCK OUTPUT SIGNALS OUTPUT SI...

Page 1356: ...0MHz3 2 clock input sample time 4 Accuracy tested and guaranteed at VRH VRL 5 0 V 0 25 V 5 This parameter is periodically sampled rather than 100 tested 6 Absolute error includes 1 2 count 2 5 mV of...

Page 1357: ...use the larger of the calculated values The diode drop voltage is a function of current and varies approximately 0 4 to 0 8 V over temperature 15 This parameter is periodically sampled rather 100 test...

Page 1358: ...2 TC SCK 2 ns ns 112 Clock SCK High or Low Time Master Slave3 tSW 2 TC 60 2 TC n 255 TC ns ns 113 Sequential Transfer Delay Master Slave Does Not Require Deselect tTD 17 TC 13 TC 8192 TC ns ns 114 Da...

Page 1359: ...ing is tested to the 5 V levels outlined in XrefBlue Table G 6 on page G 7 2 TC is defined to be the clock period 3 For high time n External SCK rise time for low time n External SCK fall time Table G...

Page 1360: ...MSB OUT MSB IN MSB OUT DATA LSB OUT PORT DATA PCS 0 3 OUTPUT PD MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 111 110 113 121 120 112 109 114 115 111 120 121 119 118 121 120 OUTPUT MSB MSB MSB O...

Page 1361: ...LSB OUT PD MSB OUT MSB IN MSB OUT MSB IN DATA LSB IN SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT MISO OUTPUT MOSI INPUT 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 DATA SLAV...

Page 1362: ...22b QGPIO 0 3 MPIO32B 11 12 rise time Input t RI 1 ms Output PDMCR SLRC0 0 50 pF Load1 t RO 50 ns Output PDMCR SLRC0 1 50 pF Load t RO 21 ns 122c SGPIOC 0 5 rise time 2 Input t RI 1 s Output SCCR COM...

Page 1363: ...2 These are 2 6 V GPIO pins Table G 20 TPU3 Timing Note TA TL to TH Num Rating Symbol Min Max Unit 124 Slew Rate of TPU Output Channel Valid1 2 SLRC0 of PDMCR 0 50 pF to 200 pF load SLRC0 of PDMCR 1...

Page 1364: ...of PDMCR 0 50 pF SLRC1 bit of PDMCR 1 tRI tRO 1 50 100 25 s ns ns ns 130 Fall Time Input Output 50 pF load SLRC1 bit of PDMCR 0 200 pF load SLRC1 bit of PDMCR 0 50 pF SLRC1 bit of PDMCR 1 tFI tFO 1 5...

Page 1365: ...tal 0 to VDD slew rate 139 Rise Time Input Output 2 6V PPM pads PDMCR2 PPMV 0 5V PPM pads PDMCR2 PPMV 1 tHI tRO 1 7 15 s ns ns 140 Fall Time Input Output 2 6V PPM pads PDMCR2 PPMV 0 5V PPM pads PDMCR2...

Page 1366: ...with the old value in the MCPSMSCR_PSL 3 0 before reloading the new value into the counter tCPSMC MCPSMSCR_PSL 3 0 1 System Clock Cycles Table G 24 MPWMSM Timing Characteristics Note All delays are i...

Page 1367: ...x2 and MPWMSCR_CP 7 0 0xFF 3 Excluding the case where the output is always 0 4 With MPWMSM enabled before enabling the MCPSM Please also see NOTE 1 on the MCPSM timing information 5 The exact timing f...

Page 1368: ...ystem clock periods Characteristic Symbol Min Max MMCSM input pin period tPPER 4 MMCSM pin low time tPLO 2 MMCSM pin high time tPHI 2 clock pin to counter bus increment tPCCB 1 2 load pin to new count...

Page 1369: ...MCPSMSCR_PSL 255 MMCSMSCR_CP MCPSMSCR_PSL 1 3 1 Minimum output resolution depends on MMCSM and MCPSM prescaler settings 2 Maximum resolution is obtained by setting CPSMPSL 3 0 0x2 and MMCSMSCR_CP 7 0...

Page 1370: ...elect to Counter Bus Increment Timing Diagram G 21 3 MDASM Timing Characteristics Table G 26 MDASM Timing Characteristics Note All delays are in system clock periods Characteristics Symbol Min Max Inp...

Page 1371: ...r Bus to pin change tCBP 3 Counter Bus to interrupt flag set tCBFLG 3 1 If the counter bus capture occurs when the counter bus is changing then the capture is delayed one cycle In situations where the...

Page 1372: ...t Pin to MDASM Interrupt Flag Timing Diagram Figure G 59 MDASM Minimum Output Pulse Width Timing Diagram Figure G 60 Counter Bus to MDASM Output Pin Change Timing Diagram fSYS MDAI input pin tPCAP Cou...

Page 1373: ...eristic Symbol Min Max Input Mode MPIOSM input pin period tPPER 1 1 The minimum input pin period pin low and pin high times depend on the rate at which the MPIOSM_DR register is polled MPIOSM pin low...

Page 1374: ...nt USIU ADDR SGPIOA 8 31 addr_sgpioa8 AF9 addr_sgpioa9 AF8 addr_sgpioa10 AC6 addr_sgpioa11 Y4 addr_sgpioa12 Y3 addr_sgpioa13 AD7 addr_sgpioa14 AE7 addr_sgpioa15 AF7 addr_sgpioa16 AD8 addr_sgpioa17 AE8...

Page 1375: ...d11 AC17 data_sgpiod12 AC18 data_sgpiod13 AD18 data_sgpiod14 AC20 data_sgpiod15 AD19 data_sgpiod16 AD20 data_sgpiod17 AE20 data_sgpiod18 AF20 data_sgpiod19 AE19 data_sgpiod20 AF19 data_sgpiod21 AE18 d...

Page 1376: ...ll_sel R26 TSIZ 0 1 tsiz0 V4 tsiz1 W1 RD WR rd_wr _b V1 BURST burst Y1 BDIP bdip_b W4 TS ts_b W2 TA ta_b W3 TEA tea_b V3 RSTCONF TEXP rstconf_b_texp Y25 OE oe_b V2 BI STS bi_b_sts_b Y2 CS 0 3 cs0_b U1...

Page 1377: ...XTAL xtal AD26 EXTAL extal AC26 XFC xfc AA26 CLKOUT clkout U23 EXTCLK extclk V24 ENGCLK BUCLK engclk_buclk V26 QSMCM PCS0 SS QGPIO0 pcs0_ss_b_qgpio0 N25 PCS 1 3 QGPIO 1 3 pcs1_qgpio1 N24 pcs2_qgpio2...

Page 1378: ...o32b0_mdo1 L23 VF1 MPIO32B1 MCKO vf1_mpio32b1_mcko L24 VF2 MPIO32B2 MSEI vf2_mpio32b2_msei_b M24 VFLS0 MPIO32B3 MSEO vfls0_mpio32b3_mseo_b M25 VFLS1 MPIO32B4 vfls1_mpio32b4 M26 MPIO32B5 MDO5 mpio32b5_...

Page 1379: ...m_tx0 L25 TPU_A TPU_B A_TPUCH 0 15 a_tpuch0 F3 a_tpuch1 C5 a_tpuch2 B5 a_tpuch3 A5 a_tpuch4 C6 a_tpuch5 D6 a_tpuch6 B6 a_tpuch7 A6 a_tpuch8 C7 a_tpuch9 D7 a_tpuch10 B7 a_tpuch11 A7 a_tpuch12 C8 a_tpuc...

Page 1380: ...CS5 a_t2clk_pcs5 F2 B_T2CLK PCS4 b_t2clk_pcs4 F1 QADC64E_A QADC64E_B ETRIG 1 2 PCS 6 7 etrig1_pcs6 B20 etrig2_pcs7 A20 A_AN0 ANw PQB0 a_an0_anw_pqb0 C11 A_AN1 ANx PQB1 a_an1_anx_pqb1 D11 A_AN2 ANy PQB...

Page 1381: ...PQB 4 7 b_an48_pqb4 A16 b_an49_pqb5 B16 b_an50_pqb6 C16 b_an51_pqb7 D16 B_AN 52 54 MA 0 2 PQA 0 2 b_an52_ma0_pqa0 A17 b_an53_ma1_pqa1 B17 b_an54_ma2_pqa2 C17 B_AN 55 59 PQA 3 7 b_an55_pqa3 D17 b_an56_...

Page 1382: ...emiconductor Global Power Supplies NVDDL nvddl AC10 AC15 AC19 AC4 AD3 AE2 AF1 C9 D9 Y23 VDD vdd A1 A25 AC22 AD23 AE24 AF25 B2 B24 C23 C3 D22 D4 V23 VDDH vddh AF21 AF5 C19 C22 D19 E1 F23 T25 Table G 28...

Page 1383: ...C2 C24 C26 C4 D1 D2 D23 D25 D26 D3 D5 E2 E24 E25 E26 E3 E4 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15...

Page 1384: ...352 balls in the perimeter rows and 36 ground balls in the center island for a total of 388 balls The case outline drawing is 1164 01 as shown in Figure G 63 ALTREF altref B10 VDDA vdda D10 VSSA vssa...

Page 1385: ...66 MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 Freescale Semiconductor G 79 1 NOTE Top Down View Figure G 63 MPC561 MPC563 Package Footprint 1 of 2...

Page 1386: ...66 MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 80 Freescale Semiconductor Figure G 64 MPC561 MPC563 Package Footprint 2 of 2...

Page 1387: ...FL S1 SGPIOC6_ FRZ_PTR_ B VSS VSS VSS VSS VSS VSS PCS2_QGPI O2 PCS1_QGPIO1 PCS0_SS_B_ QGPIO0 A_CNRX0 N P IRQ4_B_AT 2_SGPIOC4 IRQ2_B_C R_B_SGPI OC2_MDO 5_MTS IRQ0_B_S GPIOC0_ MDO4 IRQ1_B_R SV_B_SG PIOC...

Page 1388: ...AN0_A NW_PQB 0 A_AN48_P QB4 A_AN52_ MA0_PQ A0 A_AN59_P QA7 D VSS VSS VSS VDD VSS A_TPUCH5 A_TPUCH 9 A_TPUCH13 NVDDL VDDA A_AN1_A NX_PQB1 A_AN49_P QB5 A_AN53_ MA1_PQ A1 A_AN57_P QA5 E VDDH VSS VSS VSS...

Page 1389: ...CS2_B CS3_B V RD_WR_B OE_B TEA_B TSIZ0 W TSIZ1 TS_B TA_B BDIP_B Y BURST_B BI_B_STS_ B ADDR_SG PIOA12 ADDR_SG PIOA11 AA VSS VSS VSS QVDDL AB VSS VSS QVDDL VSS AC VSS QVDDL VSS NVDDL VSS ADDR_SGP IOA10...

Page 1390: ...29 VSS VDD VSS QVDDL B A_AN59_P QA7 B_AN2_AN Y_PQB2 B_AN50_ PQB6 B_AN54_M A2_PQA2 B_AN58_P QA6 VDDH MDA11 MDA15 VDDH VDD VSS QVDDL VSS C A_AN57_P QA5 B_AN3_AN Z_PQB3 B_AN51_ PQB7 B_AN55_P QA3 B_AN59_P...

Page 1391: ...ESET_B SRESET_B PORESET_B _TRST_B KAPWR W NVDDL IRQ7_B_MODC K3 RSTCONF_B _TEXP VDDSYN Y VSS VSS VSS XFC AA QVDDL VSS VSS VSSSYN AB DATA_SG PIOD7 NVDDL DATA_SG PIOD9 DATA_SGP IOD11 DATA_SG PIOD12 NVDDL...

Page 1392: ...66 MHz Electrical Characteristics MPC561 MPC563 Reference Manual Rev 1 2 G 86 Freescale Semiconductor...

Page 1393: ...ug enable register 23 43 DMBR dual mapping base register 10 36 DPDR development port data register 23 53 DPTRAM module configuration register DPTMCR 20 3 ram base address register RAMBAR 20 4 DSCR TPU...

Page 1394: ...terrupt timer register 6 45 PLPRCR PLL low power and reset control register 8 33 Port data direction registers 13 14 14 13 Port data registers 13 13 14 12 PORTQS port QS data register 15 12 PPMMCR mod...

Page 1395: ...1 TPU3 channel priority register 1 19 18 CRAM_RBAx CALRAM region base address regis ter 22 16 CRAMMCR CALRAM module configuration regis ter 22 13 CRAMOVL CALRAM overlay configuration regis ter 22 17 D...

Page 1396: ...register 23 46 CRAM_RBAx CALRAM region base address regis ter 22 15 CRAMMCR CALRAM module configuration regis ter 22 13 CRAMOVL CALRAM overlay configuration regis ter 22 17 DEC decrementer register 6...

Page 1397: ...8 QASR status register 0 14 22 QASR status registers 13 20 QSMCM configuration register QMCMMCR 15 8 interrupt level registers QDSCI_IL QSPI_IL 15 9 port QS data register PORTQS 15 11 PORTQS data dire...

Page 1398: ...7 System configuration and protection registers 6 24 System configuration registers 6 24 System protection registers 6 37 System timer registers 6 40 TBREF0 time base reference registers 6 41 TBSCR ti...

Page 1399: ...T TBREF0 ime base reference registers 6 41 TBREF1 time base reference register 1 6 41 TBSCR time base control and status register 6 42 TESR transfer error status register 6 39 TICR TPU3 interrupt con...

Page 1400: ...MPC561 MPC563 Reference Manual Rev 1 2 RegIndex 8 Freescale Semiconductor sensor register 8 37 X XER integer exception register 3 18...

Page 1401: ...imitives 3 43 B BAR 3 60 23 53 Base ID mask bits 16 32 16 33 Baud clock 15 52 BB 9 7 BBCMCR 4 19 BDIP 9 5 BE bit 3 21 Beginning of queue 2 BQ2 13 19 14 20 BG 9 7 BI 9 7 9 40 Binary divider 13 47 14 48...

Page 1402: ...control cycles 9 45 single beat transfer single beat read flow 9 9 single beat write flow 9 9 9 11 single beat transfer 9 9 storage reservation 9 42 termination signals 9 40 bus operations 9 8 bus tr...

Page 1403: ...38 Comparator A D value registers 23 41 Comparator E F value registers 23 46 Comparator G H value registers 23 47 Compare instructions 3 17 Compare size 23 48 Compare type 23 47 23 51 A 17 Completed q...

Page 1404: ...menter register 3 23 decrementer 6 18 Decrementer exception 3 53 deep sleep 6 23 Delay after transfer DT 15 24 15 36 before SCK DSCKL 15 19 DER 23 43 23 53 Development Port trap enable selection 23 52...

Page 1405: ...nt timing 19 3 Exception cause register 23 41 Exception prefix 3 21 3 22 exception table 4 7 Exceptions 3 34 alignment 3 49 classes 3 35 decrementer 3 53 external interrupt 3 48 little endian mode 3 2...

Page 1406: ...34 FP bit 3 21 FPECR 3 26 FPRF 3 15 FPRs 3 12 FPSCK 19 20 FPSCR 3 13 FPU 3 5 FPUVE 23 42 FPUVEE 23 44 FQCLK 13 47 14 48 FQD D 35 FQM D 10 FR 3 15 Frame size 15 58 Frames overload 16 17 remote 16 17 F...

Page 1407: ...6 10 Initial sample time 13 35 14 36 Input sample time IST 13 31 13 49 14 32 Instruction pipeline 3 38 sequencer 3 3 set summary 3 28 timing 3 37 Instruction fetch show cycle control 23 1 instruction...

Page 1408: ...TPU 19 11 LR 3 5 3 19 LSB 13 36 14 38 LSU 3 4 3 6 LW0EN 23 49 LW0IA 23 49 LW0IADC 23 49 LW0LA 23 49 LW0LADC 23 49 LW0LD 23 49 LW0LDDC 23 49 LW1EN 23 49 LW1IA 23 49 LW1IADC 23 49 LW1LA 23 50 LW1LADC 23...

Page 1409: ...22 4 censorship modes of UC3F 21 31 clock frequency for each 8 17 code decompression A 14 debug operation of BBC 4 7 DECRAM standby operation 4 14 disabled 13 41 14 42 DPTRAM operation 20 6 external m...

Page 1410: ...ustration 9 30 Operating Environment Architecture Book 3 branch processor 3 44 exceptions 3 45 fixed point processor special purpose registers 3 44 fixed point processor 3 44 optional facilities and i...

Page 1411: ...rity CALRAM overlay regions 22 11 channel service 19 4 Privilege level 3 7 3 21 Processor version register 3 25 Program 3 51 exception 3 51 Programmable channel service priority 19 4 transfer length 1...

Page 1412: ...ster SPSR 15 42 Queue 13 37 14 38 1 completion flag CF1 13 21 14 22 1 completion interrupt enable CIE1 13 16 14 17 1 operating mode MQ1 13 16 14 17 1 pause flag PF1 13 22 14 23 1 pause interrupt enabl...

Page 1413: ...nt exception cause register FPECR 3 26 floating point status and control register FPSCR 3 13 general purpose registers GPRs 3 12 general SPRs 3 24 hard reset configuration word register UC3FCFIG 21 16...

Page 1414: ...egister RWA 24 13 READI upload download information register UDI 24 15 READI user base address register UBA 24 12 real time clock alarm register RTCAL 6 44 real time clock register RTC 6 43 real time...

Page 1415: ...30 RETRY 9 45 RF 13 75 14 73 RIE 15 48 RJURR 13 33 14 35 RJW 16 13 16 30 RN field 3 16 RSR 7 5 RSV 9 38 RT 15 57 RTC 6 19 RTC register 6 43 RTCAL 6 44 RTCSC 6 42 RTR 16 5 16 17 RTR field 16 6 RWA 24 1...

Page 1416: ...6 37 SISR3 6 37 SIU interrupt pending registers SIPEND 6 32 SIU signals 9 4 SIUMCR 6 25 SIVEC 6 35 SIW0EN 23 52 A 17 SIW1EN 23 52 A 17 SIW2EN 23 52 A 17 SIW3EN 23 52 A 17 Slave Select SS 15 42 Slave s...

Page 1417: ...9 13 11 14 8 14 10 SUSG 23 48 SUSH 23 48 SWSR 6 38 SWT 6 21 Synchronized pulse width modulation SPWM D 48 SYPCR 6 37 SYSE 23 42 SYSEE 23 44 System call exception 3 54 system clock output 9 8 system r...

Page 1418: ...19 5 microengine 19 2 operation 19 3 coherency 19 4 emulation support 19 4 event timing 19 3 interchannel communication 19 4 programmable channel service priority 19 4 parameter RAM 19 2 19 23 addres...

Page 1419: ...niversal asynchronous receiver transmitter UART D 12 parameters receiver parameters D 13 transmitter parameters D 12 Unordered exceptions 3 35 User Instruction Set Architecture Book 1 instruction fetc...

Page 1420: ...INT 16 35 WAKEINT 16 18 16 35 WAKEMSK 16 18 Wakeup address mark WAKE 15 47 15 59 watchpoint counters 23 19 watchpoints and breakpoints 23 9 Wired OR mode for QSPI pins WOMQ 15 18 for SCI pins WOMS 15...

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