MPC563XM Reference Manual, Rev. 1
948
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Figure 23-81. T4 timing
23.6.1.2
Input/Output Signal Delays
The synchronizer, filter and edge detection logic delay the input signal transitions.
The Filter Delay varies with the filter clock (ETPUECR field FPSCK) and the filter mode used, as shown
in the
. For any given transition, it depends on the phase of the filter clock when the input
transition happens. In integration mode (TCRCLK filtering only), it also depends on the state of the
integrator counter. The Total Delay is defined as the number of system clock rising edges between the
input transition and the setting of TDL1/2, TCR1/2 incrementing, or EAC tooth sensing (TCRCLK) in
angle mode. The synchronizer delay is 2 or 3 system clocks, depending on the phase of the synchronizer
when the input transition happens. The edge detection takes 1 more system clock. The total delays are,
thus:
Min. Total Delay = Min. Synchronizer Delay + Min. Filter Delay + Edge Detection Delay
Min. Total Delay = 3 + Min. Filter Delay
Max. Total Delay = Max. Synchronizer Delay + Max. Filter Delay + Edge Detection Delay
Max. Total Delay = 4 + Max. Filter Delay
The channel filters can be bypassed, so nullifying the filter delays in the equations above.
The channel output flip-flops drive the eTPU output signals directly, without any synchronous delays.
Consult the MCU SoC Guide or Reference Manual for information on additional delays added at the
integration.
T2
T4
T4
T4
T4
T4
1st
2nd
T4
T2
T4
T2
T4
T CLOCKS
SYS.CLOCK
Nth
T4
WAIT-T4
T2
μ
PC A1
A2
T2
T2
A2
T4
A3
T4
(A1)
(A1)
(A2)
μ
INST
