MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3
provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
2.2.1
Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (V
DD
and AV
DD
) and I/O supply voltages
(GV
DD
, LV
DD
, and OV
DD
) to be applied in any particular order. During the power ramp up, before the
power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period
of time that all input and output pins will actively be driven and cause contention and excessive current.
In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core
voltage (V
DD
) before the I/O voltage (GV
DD
, LV
DD
, and OV
DD
) and assert PORESET before the power
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V, see
Figure 5
.
Table 3. Output Drive Capability
Driver Type
Output Impedance (
Ω
)
Supply Voltage
Local bus interface utilities signals
42
OV
DD
= 3.3 V
PCI signals
25
PCI output clocks (including PCI_SYNC_OUT)
42
DDR signal
20
36 (half-strength mode)
1
1
DDR output impedance values for half strength mode are verified by design and not tested.
GV
DD
= 2.5 V
DDR2 signal
18
36 (half-strength mode)
1
GV
DD
= 1.8 V
10/100/1000 Ethernet signals
42
LV
DD
= 2.5/3.3 V
DUART, system control, I
2
C, SPI, JTAG
42
OV
DD
= 3.3 V
GPIO signals
42
OV
DD
= 3.3 V
LV
DD
= 2.5/3.3 V