MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
19
RESET Initialization
Table 12
provides the PLL and DLL lock times.
5.3
QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine
block’s communication interfaces.
NOTE
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting the performance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.
Table 13
lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block
core frequency for each interface.
Table 12. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μ
s
—
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
Section 22, “Clocking,”
for more information.
Table 13. QUICC Engine Block Operating Frequency Limitations
Interface
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency
1
(MHz)
Notes
Ethernet Management: MDC/MDIO
10 (max)
10
20
—
MII
25 (typ)
100
50
—
RMII
50 (typ)
100
50
—
GMII/RGMII/TBI/RTBI
125 (typ)
1000
250
—
SPI (master/slave)
10 (max)
10
20
—
UCC through TDM
50 (max)
70
8
×
F
2
MCC
25 (max)
16.67
16
×
F
2, 4
UTOPIA L2
50 (max)
800
2
×
F
2
POS-PHY L2
50 (max)
800
2
×
F
2
HDLC bus
10 (max)
10
20
—
HDLC/transparent
50 (max)
50
8/3
×
F
2, 3