MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
20
Freescale Semiconductor
DDR and DDR2 SDRAM
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8360E/58E.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 14
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GV
DD
(typ) = 1.8 V
.
UART/async HDLC
3.68 (max internal ref
clock)
115 (Kbps)
20
—
BISYNC
2 (max)
2
20
—
USB
48 (ref clock)
12
96
—
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
Table 14. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GV
DD
1.71
1.89
V
1
I/O reference voltage
MV
REF
0.49
×
GV
DD
0.51
×
GV
DD
V
2
I/O termination voltage
V
TT
MV
REF
– 0.04
MV
REF
+ 0.04
V
3
Input high voltage
V
IH
MV
REF
+ 0.125
GV
DD
+ 0.3
V
—
Input low voltage
V
IL
–0.3
MV
REF
– 0.125
V
—
Output leakage current
I
OZ
—
±10
μ
A
4
Output high current (V
OUT
= 1.420 V)
I
OH
–13.4
—
mA
—
Output low current (V
OUT
= 0.280 V)
I
OL
13.4
—
mA
—
MV
REF
input leakage current
I
VREF
—
±10
μ
A
—
Table 13. QUICC Engine Block Operating Frequency Limitations (continued)
Interface
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency
1
(MHz)
Notes