MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
21
DDR and DDR2 SDRAM
Table 15
provides the DDR2 capacitance when GV
DD
(typ) = 1.8 V.
Table 16
provides the recommended operating conditions for the DDR SDRAM component(s) of the
device when GV
DD
(typ) = 2.5 V.
Input current (0 V
≤
V
IN
≤
OV
DD
)
I
IN
—
±10
μ
A
—
Notes:
1. GV
DD
is expected to be within 50 mV of the DRAM GV
DD
at all times.
2. MV
REF
is expected to equal 0.5
×
GV
DD
, and to track GV
DD
DC variations as measured at the receiver. Peak-to-peak noise
on MV
REF
cannot exceed ±2% of the DC value.
3. V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MV
REF
. This rail should track variations in the DC level of MV
REF
.
4. Output leakage is measured with all outputs disabled, 0 V
≤
V
OUT
≤
GV
DD
.
Table 15. DDR2 SDRAM Capacitance for GV
DD
(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
C
IO
6
8
pF
1
Delta input/output capacitance: DQ, DQS, DQS
C
DIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GV
DD
= 1.8 V ± 0.090 V, f = 1 MHz, T
A
= 25°C, V
OUT
= GV
DD
/2, V
OUT
(peak-to-peak) = 0.2 V.
Table 16. DDR SDRAM DC Electrical Characteristics for GV
DD
(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GV
DD
2.375
2.625
V
1
I/O reference voltage
MV
REF
0.49
×
GV
DD
0.51
×
GV
DD
V
2
I/O termination voltage
V
TT
MV
REF
– 0.04
MV
REF
+ 0.04
V
3
Input high voltage
V
IH
MV
REF
+ 0.18
GV
DD
+ 0.3
V
—
Input low voltage
V
IL
–0.3
MV
REF
– 0.18
V
—
Output leakage current
I
OZ
—
±10
μ
A
4
Output high current (V
OUT
= 1.95 V)
I
OH
–15.2
—
mA
—
Output low current (V
OUT
= 0.35 V)
I
OL
15.2
—
mA
—
MV
REF
input leakage current
I
VREF
—
±10
μ
A
—
Input current (0 V
≤
V
IN
≤
OV
DD
)
I
IN
—
±10
μ
A
—
Notes:
1. GV
DD
is expected to be within 50 mV of the DRAM GV
DD
at all times.
2. MV
REF
is expected to be equal to 0.5
×
GV
DD
, and to track GV
DD
DC variations as measured at the receiver. Peak-to-peak
noise on MV
REF
may not exceed ±2% of the DC value.
3. V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV
REF
. This rail should track variations in the DC level of MV
REF
.
4. Output leakage is measured with all outputs disabled, 0 V
≤
V
OUT
≤
GV
DD
.
Table 14. DDR2 SDRAM DC Electrical Characteristics for GV
DD
(typ) = 1.8 V (continued)
Parameter/Condition
Symbol
Min
Max
Unit
Notes