MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
22
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 17
provides the DDR capacitance when GV
DD
(typ) = 2.5 V.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 18
provides the input AC timing specifications for the DDR2 SDRAM interface when
GV
DD
(typ) = 1.8 V.
Table 19
provides the input AC timing specifications for the DDR SDRAM interface when
GV
DD
(typ) = 2.5 V.
Table 17. DDR SDRAM Capacitance for GV
DD
(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
C
IO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
C
DIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GV
DD
= 2.5 V ± 0.125 V, f = 1 MHz, T
A
= 25
°
C, V
OUT
= GV
DD
/2, V
OUT
(peak-to-peak) = 0.2 V.
Table 18. DDR2 SDRAM Input AC Timing Specifications for GV
DD
(typ) = 1.8 V
At recommended operating conditions with GV
DD
of 1.8 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
V
IL
—
MV
REF
– 0.25
V
—
AC input high voltage
V
IH
MV
REF
+ 0.25
—
V
—
Table 19. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GV
DD
of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
V
IL
—
MV
REF
– 0.31
V
—
AC input high voltage
V
IH
MV
REF
+ 0.31
—
V
—
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0
≤
n
≤
7)
or ECC (MECC[{0...7}] if n = 8).