MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
30
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 10
shows the GMII transmit AC timing diagram.
Figure 10. GMII Transmit AC Timing Diagram
8.2.1.2
GMII Receive AC Timing Specifications
Table 28
provides the GMII receive AC timing specifications.
GTX_CLK clock fall time, (80% to 20%)
t
GTXF
—
—
1.0
ns
—
GTX_CLK125 clock period
t
G125
—
8.0
—
ns
2
GTX_CLK125 reference clock duty cycle measured at
LV
DD/2
t
G125H
/t
G125
45
—
55
%
2
Notes:
1. The symbols used for timing specifications follow the pattern t
(first two letters of functional block)(signal)(state)(reference)(state)
for inputs
and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
GTKHDV
symbolizes GMII transmit timing
(GT) with respect to the t
GTX
clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
the valid state (V) to state or setup time. Also, t
GTKHDX
symbolizes GMII transmit timing (GT) with respect to the t
GTX
clock
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
GTX
represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
convention.
3. In rev. 2.0 silicon, due to errata, t
GTKHDX
minimum and t
GTKHDV
maximum are not supported when the GTX_CLK is selected.
Refer to Errata
QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.
Table 28. GMII Receive AC Timing Specifications
At recommended operating conditions with LV
DD
/OV
DD
of 3.3 V ± 10%.
Parameter/Condition
Symbol
1
Min
Typ
Max
Unit
Notes
RX_CLK clock period
t
GRX
—
8.0
—
ns
—
RX_CLK duty cycle
t
GRXH
/t
GRX
40
—
60
%
—
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
t
GRDVKH
2.0
—
—
ns
—
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
t
GRDXKH
0.2
—
—
ns
2
RX_CLK clock rise time, (20% to 80%)
t
GRXR
—
—
1.0
ns
—
Table 27. GMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LV
DD
/OV
DD
of 3.3 V ± 10%.
Parameter/Condition
Symbol
1
Min
Typ
Max
Unit
Notes
GTX_CLK
TXD[7:0]
t
GTKHDX
t
GTX
t
GTXH
t
GTXR
t
GTXF
TX_EN
TX_ER