MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
34
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
Table 31
provides the RMII transmit AC timing specifications.
Figure 15
shows the RMII transmit AC timing diagram.
Figure 15. RMII Transmit AC Timing Diagram
Table 31. RMII Transmit AC Timing Specifications
At recommended operating conditions with LV
DD
/OV
DD
of 3.3 V ± 10%.
Parameter/Condition
Symbol
1
Min
Typ
Max
Unit
REF_CLK clock
t
RMX
—
20
—
ns
REF_CLK duty cycle
t
RMXH
/t
RMX
35
—
65
%
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
RMTKHDX
t
RMTKHDV
2
—
—
—
10
ns
REF_CLK data clock rise time
t
RMXR
1.0
—
4.0
ns
REF_CLK data clock fall time
t
RMXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t
(first three letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
RMTKHDX
symbolizes RMII
transmit timing (RMT) for the time t
RMX
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t
RMX
represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
REF_CLK
TXD[1:0]
t
RMTKHDX
t
RMX
t
RMXH
t
RMXR
t
RMXF
TX_EN