MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
38
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2.5
RGMII and RTBI AC Timing
Specifications
Table 35
presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LV
DD
of 2.5 V ± 5%.
Parameter/Condition
Symbol
1
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
t
SKRGTKHDX
t
SKRGTKHDV
–0.5
—
—
—
0.5
ns
7
Data to clock input skew (at receiver)
t
SKRGDXKH
t
SKRGDVKH
1.0
—
—
—
2.6
ns
2
Clock cycle duration
t
RGT
7.2
8.0
8.8
ns
3
Duty cycle for 1000Base-T
t
RGTH
/t
RGT
45
50
55
%
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
t
RGTH
/t
RGT
40
50
60
%
3, 5
Rise time (20–80%)
t
RGTR
—
—
0.75
ns
—
Fall time (20–80%)
t
RGTF
—
—
0.75
ns
—
GTX_CLK125 reference clock period
t
G125
—
8.0
—
ns
6
GTX_CLK125 reference clock duty cycle
t
G125H
/t
G125
47
—
53
%
—
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of t
RGT
represents the TBI (T) receive (Rx) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, t
RGT
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
RGT
of the lowest speed transitioned
between.
5. Duty cycle reference is LV
DD
/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. In rev. 2.0 silicon, due to errata, t
SKRGTKHDX
minimum is –2.3 ns and t
SKRGTKHDV
maximum is 1 ns for UCC1, 1.2 ns for UCC2
option 1, and 1.8 ns for UCC2 option 2. In rev. 2.1 silicon, due to errata, t
SKRGTKHDX
minimum is –0.65 ns for UCC2 option 1
and –0.9 for UCC2 option 2, and t
SKRGTKHDV
maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2.
Refer to Errata QE_ENET10 in
Chip Errata for the MPC8360E, Rev. 1. UCC1 does meet t
SKRGTKHDX
minimum for rev. 2.1
silicon.