MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
50
Freescale Semiconductor
JTAG
Figure 29
provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 29. AC Test Load for the JTAG Interface
Figure 30
provides the JTAG clock input timing diagram.
Figure 30. JTAG Clock Input Timing Diagram
Figure 31
provides the TRST timing diagram.
Figure 31. TRST Timing Diagram
Figure 32
provides the boundary-scan timing diagram.
Figure 32. Boundary-Scan Timing Diagram
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω
JTAG
t
JTKHKL
t
JTGR
External Clock
VM
VM
VM
t
JTG
t
JTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
VM
t
TRST
VM = Midpoint Voltage (OVDD/2)
VM
VM
t
JTDVKH
t
JTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
t
JTKLDX
t
JTKLDZ
t
JTKLDV
Input
Data Valid
Output Data Valid