MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
61
TDM/SI
17.2
TDM/SI AC Timing Specifications
Table 58
provides the TDM/SI input and output AC timing specifications.
Figure 44
provides the AC test load for the TDM/SI.
Figure 44. TDM/SI AC Test Load
Figure 45
represents the AC timing from
Table 56
. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
Input low voltage
V
IL
—
–0.3
0.8
V
Input current
I
IN
0 V
≤
V
IN
≤
OV
DD
—
±10
μ
A
Table 58. TDM/SI AC Timing Specifications
1
Characteristic Symbol
2
Min
Max
3
Unit
TDM/SI outputs—External clock delay
t
SEKHOV
2
10
ns
TDM/SI outputs—External clock high impedance
t
SEKHOX
2
10
ns
TDM/SI inputs—External clock input setup time
t
SEIVKH
5
—
ns
TDM/SI inputs—External clock input hold time
t
SEIXKH
2
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
SEKHOX
symbolizes the TDM/SI
outputs external timing (SE) for the time t
TDM/SI
memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx]. See
the
MPC8360E Integrated Communications Processor Family Reference Manual for more details.
Table 57. TDM/SI DC Electrical Characteristics (continued)
Characteristic
Symbol
Condition
Min
Max
Unit
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω