MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
65
HDLC, BISYNC, Transparent, and Synchronous UART
19.2
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
Table 62
and
Table 63
provide the input and output AC timing specifications for HDLC, BISYNC,
transparent, and synchronous UART protocols.
Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications
1
Characteristic Symbol
2
Min
Max
Unit
Outputs—Internal clock delay
t
HIKHOV
0
11.2
ns
Outputs—External clock delay
t
HEKHOV
1
10.8
ns
Outputs—Internal clock high impedance
t
HIKHOX
-0.5
5.5
ns
Outputs—External clock high impedance
t
HEKHOX
1
8
ns
Inputs—Internal clock input setup time
t
HIIVKH
8.5
—
ns
Inputs—External clock input setup time
t
HEIVKH
4
—
ns
Inputs—Internal clock input hold time
t
HIIXKH
1.4
—
ns
Inputs—External clock input hold time
t
HEIXKH
1
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
HIKHOX
symbolizes the outputs
internal timing (HI) for the time t
serial
memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 63. Synchronous UART AC Timing Specifications
1
Characteristic Symbol
2
Min
Max
Unit
Outputs—Internal clock delay
t
UAIKHOV
0
11.3
ns
Outputs—External clock delay
t
UAEKHOV
1
14
ns
Outputs—Internal clock high impedance
t
UAIKHOX
0
11
ns
Outputs—External clock high impedance
t
UAEKHOX
1
14
ns
Inputs—Internal clock input setup time
t
UAIIVKH
6
—
ns
Inputs—External clock input setup time
t
UAEIVKH
8
—
ns
Inputs—Internal clock input hold time
t
UAIIXKH
1
—
ns
Inputs—External clock input hold time
t
UAEIXKH
1
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
HIKHOX
symbolizes the outputs
internal timing (HI) for the time t
serial
memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).