MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
66
Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 49
provides the AC test load.
Figure 49. AC Test Load
19.3
AC Test Load
Figure 50
and
Figure 51
represent the AC timing from
Table 62
and
Table 63
. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
Figure 50
shows the timing with external clock.
Figure 50. AC Timing (External Clock) Diagram
Figure 51
shows the timing with internal clock.
Figure 51. AC Timing (Internal Clock) Diagram
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω
Serial CLK (Input)
t
HEIXKH
t
HEIVKH
t
HEKHOV
Input Signals:
(See Note)
Output Signals:
(See Note)
t
HEKHOX
Note:
The clock edge is selectable.
Serial CLK (Output)
t
HIIXKH
tHIKHOV
Input Signals:
(See Note)
t
HIIVKH
t
HIKHOX
Note:
The clock edge is selectable.
Output Signals:
(See Note)