MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
85
Clocking
22 Clocking
Figure 54
shows the internal distribution of clocks within the MPC8360E.
Figure 54. MPC8360E Clock Subsystem
Core PLL
System
DDRC2
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MEMC2_MCK[0:1]
MEMC2_MCK[0:1]
core_clk
e300 Core
csb_clk to Rest
CLKIN
csb_clk
MPC8360E
DDRC2
Memory
Local Bus
PCI_CLK_OUT[0:2]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the Device
lb_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
To Local
Bus/DDRC2
Controller
DLL
/2
Divider
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
DDRC1
/2
ddr1_clk
DDRC1
Memory
Device
PLL
QUICC
PLL
ce_clk to QUICC Engine Block
Engine