MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
88
Freescale Semiconductor
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
Table 68
specifies which units have a configurable clock
frequency.
Table 69
provides the operating frequencies for the TBGA package under recommended operating
conditions (see
Table 2
). All frequency combinations shown in the table below may not be available.
Maximum operating frequencies depend on the part ordered, see
Section 25.1, “Part Numbers Fully
Addressed by this Document,”
for part ordering details and contact your Freescale sales representative or
authorized distributor for more information.
Table 68. Configurable Clock Units
Unit
Default
Frequency
Options
Security core
csb_clk
/3
Off,
csb_clk
1
, csb_clk
/2,
csb_clk
/3
1
With limitation, only for slow csb_clk rates, up to 166 MHz.
PCI and DMA complex
csb_clk
Off,
csb_clk
Table 69. Operating Frequencies for the TBGA Package
Characteristic
1
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
csb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
400 MHz
533 MHz
667 MHz
2
2
The 667 MHz core frequency is based on a 1.3 V V
DD
supply voltage.
Unit
e300 core frequency (
core_clk)
266–400
266–533
266–667
MHz
Coherent system bus frequency (
csb_clk)
133–333
MHz
QUICC Engine frequency
3
(
ce_clk)
3
The 500 MHz QE frequency is based on a 1.3 V V
DD
supply voltage.
266–500
MHz
DDR and DDR2 memory bus frequency (MCLK)
4
4
The DDR data rate is 2x the DDR memory bus frequency.
100–166.67
MHz
Local bus frequency (LCLK
n)
5
5
The local bus frequency is 1/2, 1/4, or 1/8 of the
lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66.67
MHz
Security core maximum internal operating frequency
133
133
166
MHz