MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
89
Clocking
22.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters.
Table 70
shows the
multiplication factor encodings for the system PLL.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in
Table 71
.
NOTE
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600–1400 MHz.
Table 70. System PLL Multiplication Factors
RCWL[SPMF]
System PLL
Multiplication Factor
0000
× 16
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111
× 7
1000
× 8
1001
× 9
1010
× 10
1011
× 11
1100
× 12
1101
× 13
1110
× 14
1111
× 15
Table 71. System PLL VCO Divider
RCWL[SVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved