MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
95
Clocking
22.4
Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC
Engine block PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock.
Table 76
shows suggested PLL configurations for 33 and 66 MHz input clocks and
illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to
Section 22, “Clocking,”
for the appropriate operating frequencies for your
device.
Table 76. Suggested PLL Configurations
Conf
No.
1
SPMF
CORE
PLL
CEPMF
CEPDF
Input
Clock Freq
(MHz)
CSB Freq
(MHz)
Core Freq
(MHz)
QUICC
Engine
Freq (MHz)
400
(MHz)
533
(MHz)
667
(MHz)
33 MHz CLKIN/PCI_SYNC_IN Options
s1
0100
0000100
æ
æ
33
133
266
—
∞
∞
∞
s2
0100
0000101
æ
æ
33
133
333
—
∞
∞
∞
s3
0101
0000100
æ
æ
33
166
333
—
∞
∞
∞
s4
0101
0000101
æ
æ
33
166
416
—
—
∞
∞
s5
0110
0000100
æ
æ
33
200
400
—
∞
∞
∞
s6
0110
0000110
æ
æ
33
200
600
—
—
—
∞
s7
0111
0000011
æ
æ
33
233
350
—
∞
∞
∞
s8
0111
0000100
æ
æ
33
233
466
—
—
∞
∞
s9
0111
0000101
æ
æ
33
233
583
—
—
—
∞
s10
1000
0000011
æ
æ
33
266
400
—
∞
∞
∞
s11
1000
0000100
æ
æ
33
266
533
—
—
∞
∞
s12
1000
0000101
æ
æ
33
266
667
—
—
—
∞
s13
1001
0000010
æ
æ
33
300
300
—
∞
∞
∞
s14
1001
0000011
æ
æ
33
300
450
—
—
∞
∞
s15
1001
0000100
æ
æ
33
300
600
—
—
—
∞
s16
1010
0000010
æ
æ
33
333
333
—
∞
∞
∞
s17
1010
0000011
æ
æ
33
333
500
—
—
∞
∞
s18
1010
0000100
æ
æ
33
333
667
—
—
—
∞
c1
æ
æ
01001
0
33
—
—
300
∞
∞
∞
c2
æ
æ
01100
0
33
—
—
400
∞
∞
∞
c3
æ
æ
01110
0
33
—
—
466
—
∞
∞
c4
æ
æ
01111
0
33
—
—
500
—
∞
∞