MPC8572E Advanced Mezzanine Card Hardware Getting Started Guide, Rev. 1.0
Freescale Semiconductor
5
Check Switches
SW5.5
OFF
[SW5.5:6] = OFF:ON. e500 Core #1:CCB = 2:1
SW5.6
ON
SW5.7
OFF
[SW5.7:8] = OFF:OFF. Boot ROM Location = 32-bit Local FLASH Memory
SW5.8
OFF
SW500
SW500.1
ON
[SW500.1:3]=ON:ON:OFF.DDR Clock Ratio = 10:1 DDRCLK (666 MHz)
SW500.2
ON
SW500.3
OFF
SW500.4
OFF
[SW500.4:5] = OFF:OFF. MPC8572E acts as the host processor
SW500.5
OFF
SW500.6
ON
[SW500.6:8] = ON:ON:OFF. IO Port Selection = SRIO 125 MHz, 3.125 Gbps (x4)
SW500.7
ON
SW500.8
OFF
SW501
SW501.1
OFF
[SW501.1] = OFF Boot Sequence Configuration = Boot Sequencer Disabled
SW501.2
OFF
CPU Boot Config:
[SW501.2:3] = OFF:ON. E500 Core 0 allowed to boot, Core 1 in boot hold-off
SW501.3
ON
SW501.4
ON
RIO System Size:
[SW501.4] = ON. Large system size, up to 65,536 devices
Table 3. Header Configuration/Availability
Feature
Status
Comments
J1
Available
IEEE Std 1588™ header
J2
Available
USB DUART Connection. Provides debug information from MPC8572E Core #0 /1.
J3
—
MMC BDM Debug header. Reserved for factory use only.
J4
Available
COP Debug Header
J6
—
CPLD JTAG Select. Reserved for factory use only.
J7
Available
Pin 1 = TxD, Pin 2 = RxD, Pin 3 = GND. Connect for console debug information from MMC only.
HD1
—
CPLD Programming Header. Reserved for factory use only.
Table 2. Default Switch Settings (continued)
Feature
Default Settings
[OFF = 1, ON = 0)
Comments
