Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
4-17
4.7.2
CLASS Priority Mapping Registers (CnPMRx)
CnPMRx is used as a look-up table for mapping the priority received from the initiator. By default the
input priority is mapped to an identical value on the output. This register also enables/disables the priority
derivation feature.
Note:
You cannot write to this register while there are open CLASS transactions.
WS
10–8
0
Wrap Size
These bits define how the normalizer
segments the access when the target
expect wrapping access. The normalizer
can segment the access to avoid wrapping
when these bits are set.
Notes: 1.
These bits are
unimplemented in CLASS 2
and are reserved.
2.
The number of bytes cannot
exceed 512 bytes.
Therefore, if the transaction
uses a data bus width of 128
bits, configuring WS of 5, 6,
or 7 effectively selects the
value of 32 datums.
000
Disabled.
001
2 datums.
010
4 datums.
011
8 datums.
100
16 datums.
101
32 datums.
110
64 datums.
111
128 datums.
—
7–4
0
Reserved. Write to 0 for future compatibility.
RC
3–0
0
Response Control
Because accesses can be segmented and
have a few target accesses, the
end-of-transmission (EOT) attributes are
accumulated. The normalizer has four bits
that defined the accumulated EOT
attributes. This bit defines the
methodology to use to evaluate the EOT
accumulation.
Note:
This bit is not implemented in
CLASS2 and is reserved.
0
Set the segment bit if the relevant EOT attribute is
high.
1
Clear the segment bit if the relevant EOT attribute is
low.
Note:
When MBS, BA, FSP, PB, WS, and DA are all 0, the normalizer works in sampler mode.
C0PMR[0–5]
CLASS Priority Mapping Registers
Offset 0x800 + x*0x04
C1PMR[0–5]
C2PMR[0–3]
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
PB
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
PM3
—
PM2
—
PM1
—
PM0
Type
R/W
Reset
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Table 4-3. CnMTCRx Bit Descriptions (Continued)
Name
Reset
Description
Settings
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
