Enhanced Queued Analog-to-Digital Converter (EQADC)
27-98
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27.7.6.3
Time Stamp Feature
The on-chip ADCs can provide a time stamp for the conversions they execute. A time stamp is the value
of the time base counter latched when the EQADC detects the end of the analog input voltage sampling.
A time stamp for a conversion command is requested by setting the TSR bit in the corresponding
command. When TSR is negated, that is a time stamp is not requested, the ADC returns a single result
message containing the conversion result. When TSR is asserted, that is a time stamp is requested, the
ADC returns two result messages; one containing the conversion result, and afterwards another containing
the time stamp for that conversion. The result messages are sent in this order to the RFIFOs and both
messages are sent to the same RFIFO was specified in the MESSAGE_TAG field of the executed
conversion command.
The time base counter is a 16-bit up counter that wraps after reaching 0xFFFF. It is disabled after reset and
it is enabled according to the setting of TBC_CLK_PS field in
Section 27.6.3.2, ADC Time Stamp Control
. TBC_CLK_PS defines if the counter is enabled or disabled, and, if enabled, at
what frequency it is incremented. The time stamps are returned regardless of whether the time base counter
is enabled or disabled. The time base counter can be reset by writing 0x0000 to the
Time Base Counter Registers (ADC_TBCR)
, with a write configuration command.
27.7.6.4
ADC Pre-gain Feature
Each ADC can be configured to have a selectable input gain as defined in
Configuration 1-8 Control Registers (ADC_ACR1-8)
. This means the input signal is sampled and the
result is amplified by factor 2, or 4 before the conversion phase. In present implementation of this feature,
the conversion is 1 or 2 ADC clock cycles longer for gain 2 or gain 4, respectively.
27.7.6.5
ADC Resolution Selection Feature
The ADCs conversion resolutions can be 8 bits, 10 bits or 12 bits as described in
Alternate Configuration 1-8 Control Registers (ADC_ACR1-8)
. For conversions at a resolution less than
12, the ADC is executing less operations and the conversion time is smaller. In this ADC, it is verified that
0b10110
46
2.61 MHz
174 Ksps
163 Ksps
0b10111
48
2.5 MHz
167 Ksps
156 Ksps
0b11000
50
2.4 MHz
160 Ksps
150 Ksps
0b11001
52
2.31 MHz
154 Ksps
144 Ksps
0b11010
54
2.22 MHz
148 Ksps
139 Ksps
0b11011
56
2.14 MHz
143 Ksps
134 Ksps
0b11100
58
2.07 MHz
138 Ksps
129 Ksps
0b11101
60
2.0 MHz
133 Ksps
125 Ksps
0b11110
62
1.94 MHz
129 Ksps
121 Ksps
0b11111
64
1.88 MHz
125 Ksps
117 Ksps
Table 27-40. ADC Clock Configuration Example (Platform Clock Frequency=120 MHz) (continued)
ADC0/1_CLK_PS[0:4]
Platform Clock
Divide Factor
ADC Clock
(Platform Clock
= 120 MHz)
Differential
Conversion Speed
with Default Sampling
Time (2 cycles)
Single-Ended
Conversion Speed
with Default Sampling
Time (2 cycles)
Summary of Contents for PXR4030
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