Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-9
PXR40 Microcontroller Reference Manual, Rev. 1
— global parameter address mode allows access to common Channel data of up to 256 32-bit
parameters (1024 bytes)
— support for indirect and stacked data access schemes.
— parallel execution of: data access, ALU, Channel control and flow control subinstructions in
selected combinations.
— 32-bit microengine registers and 24-bit resolution ALU, with 1 microcycle addition and
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands;
single bit manipulation, shift operations, sign extension and conditional execution.
— additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned
Multiply/MAC combinations, and unsigned 24-bit Divide. The MAC/Divide unit works in
parallel with the regular microcode commands.
•
Resource sharing features support channel sharing of channel registers, memory and microengine
time:
— hardware Scheduler works as a “task management” unit, dispatching event service routines by
predefined, Host-configured priority.
— automatic Channel context switch when a “task switch” occurs, i.e., one Function Thread ends
and another begins to service a request from other Channel: Channel-specific registers, flags
and parameter base address are automatically loaded for the next serviced channel.
— individual channel priority setting in 3 levels: high, middle and low.
— Scheduler priority scheme allows calculation of worst case latency for event servicing and
ensures servicing all channels by preventing permanent blockage.
— SDM shared between Host CPU and both eTPU Engines, supporting communication either
between Channels and Host or inter-channel.
— hardware implementation of 4 Semaphores supports resource sharing between both eTPU
Engines.
— Hardware semaphores directly supported by the microengine instruction set.
— dual parameter coherency hardware support allows atomic (to host) access to 2 parameters by
microengine(s) in back-to-back accesses.
— coherent dual-parameter controller allows atomic (to microengines) accesses to 2 parameters
by the host.
•
Development support features:
— Nexus class 3 debug support.
— Software breakpoints.
— Debug interface supporting single-step execution, forced microinstruction execution,
Hardware breakpoints and watchpoints on several conditions.
•
Safety support features:
— SCM (code memory) continuous signature-check built-in self test (MISC - Multiple Input
Signature Calculator), runs concurrently with eTPU normal operation.
•
(more on
Section 29.1.2.3, eTPU2 Enhancements over eTPU
).
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
