Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-49
PXR40 Microcontroller Reference Manual, Rev. 1
NOTE
Interrupt and Data Transfer requests can be cleared even when Engines are
in Module Disable Mode, through the Global Channel Registers, and also
DMA completion for Data Transfer requests.
Channel Interrupts and Data Transfer Requests can only be issued by eTPU microcode, through one of the
Channel Control instruction fields (see the
eTPU Reference Manual
for details).
Both Channel Interrupt and Data Transfer requests can be individually enabled for each channel.
eTPU Interrupt and Data Transfer Registers are mirrored in two organizations: grouped by Channel and
grouped by type (interrupt status, interrupt enable, data transfer status, data transfer enable). This allows
either “channel-oriented” or “bundled channel” Host interrupt service schemes, or a combination of them.
For a detailed description, refer to
Section 29.2.8, Channel Registers Layout,
.
eTPU can also assert a
Global Exception
interrupt indicating a global illegal state. There are four possible
sources for a Global Exception:
•
Watchdog Timeout, if enabled by the ETPUWDTR register. See
.
•
Execution of an illegal instruction by the microengine (see the
eTPU Reference Manual
for
details). This Global Exception source is flagged by the bits ILF1 and ILF2 in register ETPUMCR.
•
An SCM signature mismatch detected by the Multiple Input Signature Calculator - MISC. See
Section 29.3.6.1, SCM Test - Multiple Input Signature Calculator
. This source is flagged by the bit
SCMMISF in register ETPUMCR.
•
Microcode request, through microinstruction field CIRC (see the
eTPU Reference Manual
for
details). This Global Exception source is flagged by bits MGE1(Engine A) and MGE2(Engine B)
in register ETPUMCR. The cause of this illegal state is application-dependent. The microcode may
write an error code into the SDM to indicate the cause of the exception, for instance.
Global Exceptions cannot be directly disabled within eTPU, except by disabling its sources (Memory
Error, MISC and microcode), and it is cleared by writing 1 to the GEC bit in ETPUMCR. Clearing Global
Exception clears all Global Exception source status bits (ILF1, ILF2, SCMMISF, MGE1, MGE2,
SCMERR, SDMERR). If GEC is written 1 at the same time any of the sources issues a Global Exception,
both the interrupt and the status bit of that source remains asserted. The assertion of Global Exception by
one of the sources above does not prevent the others from asserting it too, so any number of them, in any
combination, can be flagged.
NOTE
There can be a race between the clear of a Global Exception and occurrence
of a new set condition, such that the set happens just before the clear and
cannot be sensed by the Host. Therefore, Global Exception cannot be used
as a normal interrupt source: it should only be used for emergency
procedures.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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