External Bus Interface (EBI)
Freescale Semiconductor
30-39
PXR40 Microcontroller Reference Manual, Rev. 1
30.4.2.7
Size, Alignment and Packaging on Transfers
shows the allowed sizes that an internal master can request from the EBI. The behavior of the
EBI for request sizes not shown below is undefined. No error signal is asserted for these erroneous cases.
Even though misaligned non-burst transfers from internal masters are supported, the EBI naturally aligns
the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if
necessary. See
Section 30.4.2.11, Misaligned Access Support
for these cases.
Natural alignment for the EBI means:
•
Byte access can have any address
•
16-bit access, address bit 31 must be 0
•
32-bit access, address bits 30-31 must be 0
•
For burst accesses of any size, address bits 29-31 must be 0
The EBI never generates a misaligned external access, so a multi-master system with two e200-based
MCUs can never have a misaligned external access from one to the other. In the erroneous case that an
externally-initiated misaligned access does occur, the EBI errors the access (by asserting D_TEA
externally) and does not initiate the access on the internal bus.
The EBI requires that the portion of the data bus used for a transfer to/from a particular port size be fixed.
A 32-bit port must reside on data bus bits 0-31,and a 16-bit port must reside on bits 0-15.
In the following figures and tables the following convention is adopted:
•
The most significant byte of a 32-bit operand is OP0, and OP3 is the least significant byte.
•
The two bytes of a 16-bit operand are OP0 (most significant) and OP1, or OP2 (most significant)
and OP3, depending on the address of the access.
•
The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
Table 30-16. Transaction Sizes Supported by EBI
# Bytes (internal master)
1
2
4
3
1
1
Some misaligned access cases may
result in 3-byte writes. These cases
are treated as power-of-2 sized
requests by the EBI, using D_WE[0:3]
to make sure only the appropriate 3
bytes get written.
8
32
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
