Nexus Development Interface (NDI)
31-52
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
31.14.6.3 DTM Operation
31.14.6.3.1
DTM Queueing
NZ7C3 implements a message queue for DTM messages. Messages that enter the queue are transmitted
via the auxiliary pins in the order in which they are queued.
NOTE
If multiple trace messages must be queued at the same time, watchpoint
messages have the highest priority (WPM
OTM
BTM
DTM).
31.14.6.3.2
Relative Addressing
The relative address feature is compliant with the IEEE-ISTO 5001-2011 standard recommendations, and
is designed to reduce the number of bits transmitted for addresses of data trace messages. See
Section 31.14.2, Relative Addressing
for details.
Table 31-27. Data Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
At the negation of JTAG reset (JCOMP), queue pointers, counters, state machines,
and registers within the NZ7C3 module are reset. If data trace is enabled, the first
data trace message is a data write/read with sync. message.
Data Trace Enabled
The first data trace message (after data trace has been enabled) is a
synchronization message.
Exit from Low Power/Debug Upon exiting from low power or debug modes, the next data trace message is
converted to a data write/read with sync. message.
Queue Overrun
An error message occurs when a new message cannot be queued due to a full
message queue. The FIFO discards messages until it has completely emptied the
queue. After the queue is empty, an error message is queued that indicates the
message types denied queuing while the FIFO was emptying. The next DTM
message in the queue is a data write/read with sync. message.
Periodic Data Trace Sync.
A forced synchronization occurs periodically after 255 data trace messages have
been queued. A data write/read with sync. message is queued. The periodic data
trace message counter then resets.
Event In
If the Nexus module is enabled, a EVTI assertion initiates a data trace write/read
with sync. message upon the next data write/read (if data trace is enabled and the
EIC bits of the DC1 register have enabled this feature).
Attempted Access to Secure
Memory
For devices which implement security, any attempted read or write to secure
memory locations temporarily disables data trace and loses the DTM. A
subsequent read/write queues a data trace read/write with sync. message.
Collision Priority
All messages have the following priority: WPM
OTM
BTM
DTM. A DTM
message which attempts to enter the queue at the same time as a watchpoint
message or ownership trace message or branch trace message can be lost. A
subsequent read/write queues a data trace read/write with sync. message.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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