Frequency Modulated Phase-Locked Loop (FMPLL)
6-8
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
16–23
Reserved.
Note: Do not set this bit to 1.
24–31
EMFD
Enhanced Multiplication Factor Divider. The EMFD bits control the value of the divider in the PLL feedback
loop. The value specified by the EMFD bits establish the multiplication factor applied to the reference
frequency. The decimal equivalent of the EMFD binary number is substituted into the equation from
for F
sys
to determine the equivalent multiplication factor. The range of settings is
32
EMFD
132.
Note: EMFD values less than 32 and greater than 132 are invalid and cause the PLL to produce an
unpredictable clock output. The VCO frequency must be within the f
VCO
specification (see the PXR40
Microcontroller Data Sheet).
When the EMFD bits are changed, the PLL loses lock. Do not change the EMFD bits during FM operation.
Before changing EMFD, FM must be disabled and then reconfigured after the PLL re-locks to the new EMFD
value.To prevent an immediate reset, clear the LOLRE bit before writing the EMFD bits.
In PLL Off mode, the EMFD bits have no effect.
shows the available divide ratios.
Table 6-4. Pre-divider Ratios
EPREDIV
Input Divide Ratio (1)
0000
1
0001
2 (default if PLLCFG[2]=0)
0010
3
0011
4 (default if PLLCFG[2]=1)
0100
5
0101
6
0110
Invalid
0111
8
1000
Invalid
1001
10
1010–1111
Invalid
Table 6-5. Feedback Divide Ratios
EMFD
Feedback Divide Ratio (EMFD+16)
0000_0000–0001_1111
Invalid
0010_0000
48 (default for PXR40)
0010_0001
49
0010_0010
50
0010_0011
51
0010_0100
52
Table 6-3. ESYNCR1 Bit Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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