System Integration Unit (SIU)
7-40
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7.3.1.14
GPIO Pin Data Output Registers 0–512 (SIU_GPDOn)
The 8-bit SIU_GPDO
n
registers defined in
each specify the output data for the function
assigned to the GPIO[
n
] pin. The
n
notation in the SIU_GPDO
n
register name relate to the [
n
] in GPIO[
n
]
signal name. For example, SIU_GPDO246 contains the PDO246 bit for CNTXD_GPIO246. The address
for a GPDO pin is the GPIO number plus an offset of SI 0x0600.
Software writes to the SIU_GPDO
n
registers to drive data out on the external pin. Each register drives one
external pin, which allows independent control of the pin. Writes to the SIU_GPDO
n
registers have no
effect if an input function is assigned to the pin by the pad configuration register.
If the direction of a GPIO signal changes from input to output, the SIU_GPDO
n
register value is
automatically driven out to the external pin without a software update.
Writes to the SIU_GPDO
n
registers have no effect when a primary or alternate function is assigned (except
you can read the value back that was just written).
7.3.1.15
GPIO Pin Data Input Registers 0–255 (SIU_GPDIn)
NOTE
This register is implemented for legacy purposes and is limited to 256
general purpose input registers. For full access to all 512 general purpose
input registers, the SIU_GPDI
n
Data Input Registers (SIU_GPDI0_3 - SIU_GPDI508_511) - Standard
,
should be used.
The 8-bit read-only SIU_GPDI
n
each specify the input state for the
function assigned to the GPDI[
n
] pin. The
n
notation in the SIU_GPDI
n
register name relates to the [
n
] in
GPIO[
n
] signal name. For example, SIU_GPDI246 contains the PDI246 bit for CNTXD_GPIO246. The
Address: SI n
R/W
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
PDOn
W
Reset
0
0
0
0
0
0
0
0
Figure 7-15. General Purpose Data Output (GPDO) Registers 0–512 (SIU_GPDOn)
Table 7-23. SIU_GPDO Bit Field Descriptions
Field
Description
0–6
Reserved
7
PDOn
Pin data out. Stores the data to drive out the external GPIO. If the register is read,
it returns the value written.
0 A logic 0 is driven on the external GPIO pin when the pin is configured as an
output.
1 A logic 1 is driven on the external GPIO pin when the pin is configured as an
output.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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