Boot Assist Module (BAM)
Freescale Semiconductor
9-13
PXR40 Microcontroller Reference Manual, Rev. 1
– VLE instructs the MCU to program MMU entries 1–3 with VLE attribute. If it is 1, the
downloaded code must be compiled to VLE instructions, if it is 0 the code contains classic
Power Book E architecture instructions.
3. Download data.
Each byte of data received is stored in the MCU memory, starting at the START_ADDRESS
specified in the previous step. The data increments through memory until the number of bytes
stored matches CODE_LENGTH specified in the previous step.
The BAM program buffers incoming data, collecting up to eight bytes. The buffered data is written
to the RAM with 64-bit writes to prevent ECC errors, which may happen if the MCU RAM is
protected by 64-bit ECC code.
Once the buffered data is written to the RAM the BAM program refreshes the SWT.
NOTE
Only system RAM supports 64-bit writes; therefore, attempting to
download data to other RAM apart from system RAM causes errors.
If the start address of the downloaded data is not on an 8-byte boundary, the
BAM writes 0x0 to the memory locations from the proceeding 8-byte
boundary to the start address (maximum 4 bytes). The BAM also writes 0x0
to all memory locations from the last byte of data downloaded to the
following 8 byte boundary (maximum 7 bytes). An additional 8 zero bytes
are written to prevent possible ECC errors that may be caused by the CPU
pre-fetching.
The BAM appends an additional two zero double-words at the end of the
code loaded into system RAM in order to prevent possible ECC errors,
which could otherwise happen due to the CPU pre-fetching data after the
last instruction where the RAM is not initialized.
The last loaded code address must not equal or exceed 0x4003_FFF0 (the
highest RAM address allowed by MMU settings minus the two zero
double-words, written by BAM at the end of code download).
4. Switch to the loaded code.
The BAM program waits for the last echo message transmission to complete, then the active
communication controller is disabled. Its pins revert to GPIO inputs.
To provide compatibility with older devices, the BAM
– writes the core’s time base registers (TBU and TBL) with 0x0
– enables the core watchdog to cause a reset after a time-out period of 2.5 x 2
27
system clock
cycles
– disables software watchdog (SWT)
for examples of time out periods.
The BAM code passes control to the loaded code at START_ADDRESS, which was received in
step 2 of the protocol.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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