Interrupts and Interrupt Controller (INTC)
10-12
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
written to the INTC_EOIR are ignored. Those values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0’s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
10.3.1.5
INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0–7)
The INTC_SSCIR
n
support the setting or clearing of software configurable interrupt requests. These
registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With
the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral.
This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing
a 1 to SET
n
leaves SET
n
unchanged at 0 but sets CLR
n
. Writing a 0 to SET
n
has no effect. CLR
n
is the
flag bit. Writing a 1 to CLR
n
clears it. Writing a 0 to CLR
n
has no effect. If a 1 is written to a pair SET
n
and CLR
n
bits at the same time, CLR
n
is asserted, regardless of whether CLR
n
was asserted before the
write.
Although INTC_SSCI
n
is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
Address: Base + 0x0018 (INTC_EOIR)
Access: W/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
EOIR
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-11. INTC End-of-Interrupt Register (INTC_EOIR)
Address: Base + n (INTC_SSCIRn); n = 0–7
Access: R/W
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
CLRn
W
SETn
Reset
0
0
0
0
0
0
0
0
Figure 10-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn)
Table 10-6. INTC_SSCIRn Field Descriptions
Field
Description
0–5
Reserved, must be cleared.
6
SETn
Set flag bits. Writing a 1 sets the corresponding CLRn bit. Writing a 0 has no effect. Each SETn is always read as a 0.
7
CLRn
Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn clears it provided that a 1 is not written simultaneously to its
corresponding SETn bit. Writing a 0 to CLRn has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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