Interrupts and Interrupt Controller (INTC)
Freescale Semiconductor
10-31
PXR40 Microcontroller Reference Manual, Rev. 1
Clearing the peripheral interrupt request enable bit for the peripheral
initiating the request, or setting the IRQ mask bit has the same consequences
as clearing its flag bit. Setting its enable bit or clearing its mask bit while its
flag bit is asserted has the same effect on the INTC as an interrupt event
setting the flag bit.
10.4.1.1
Peripheral Interrupt Requests
An interrupt event in a peripheral’s hardware sets a flag bit which resides in that peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
10.4.1.2
Software configurable Interrupt Requests
The software set/clear interrupt registers (INTC_SSCIR
x_x
) support the setting or clearing of
software-configurable interrupt requests. These registers contain eight independent sets of bits to set and
clear a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves
the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC
just like a peripheral interrupt request.
An interrupt request is triggered by software writing a 1 to the SET
n
bit in INTC software set/clear
interrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets a CLR
n
flag bit that generates an
interrupt request. The interrupt request is cleared by writing a 1 to the CLR
n
bit. Specific behavior includes
the following:
•
Writing a 1 to SET
n
leaves SET
n
unchanged at 0 but sets the flag bit (CLR
n
bit).
•
Writing a 0 to SET
n
has no effect.
•
Writing a 1 to CLR
n
clears the flag (CLR
n
) bit.
•
Writing a 0 to CLR
n
has no effect.
•
If a 1 is written to a pair of SET
n
and CLR
n
bits at the same time, the flag (CLR
n
) is set, regardless
of whether CLR
n
was asserted before the write.
The time from the write to the SET
n
bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
10.4.1.3
Unique Vector for Each Interrupt Request Source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.
Software configurable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interrupt
requests are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.
10.4.2
Priority Management
The asserted interrupt requests are compared to each other based on their PRI
n
values in INTC priority
select registers (INTC_PSR0–INTC_PSR479). The result of that comparison also is compared to PRI in
Summary of Contents for PXR4030
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