Flash Memory Array and Control
Freescale Semiconductor
12-13
PXR40 Microcontroller Reference Manual, Rev. 1
Table 12-6. FLASH_x_LMLR Field Descriptions
Field
Description
0
LME
Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SLOCK, MLOCK and
LLOCK) to be set or cleared by register writes. This bit is a status bit only, and may not be written or
cleared, and the reset value is 0. The method to set this bit is to write a password, and if the password
matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset operation occurs.
For LME, the password 0xA1A1_1111 must be written to the FLASH_x_LMLR register.
0 Low/Mid Address Locks are disabled, and can not be modified.
1 Low/Mid Address Locks are enabled to be written.
1–10
Reserved
11
SLOCK
Shadow Lock. This bit is used to lock the shadow block from programs and erases. A value of 1 in the
SLOCK register signifies that the shadow block is locked for program and erase. A value of 0 in the
SLOCK register signifies that the shadow block is available to receive program and erase pulses. The
SLOCK register is not writable once an interlock write is completed until FLASH_x_MCR[DONE] is set
at the completion of the requested operation. Likewise, SLOCK register is not writable if a high voltage
operation is suspended. SLOCK is also not writeable during UTest operations, when AIE is high.
Upon reset, information from the shadow block is loaded into the SLOCK register. The SLOCK bit may
be written as a register. Reset causes the bits to go back to their shadow block value. The default value
of the SLOCK bits (assuming erased shadow location) is locked.
SLOCK is not writable unless LME is high.
12–13
Reserved
14–15
MLOCK[1:0]
Mid Address Space Block Lock. A value of 1 in a bit of the lock register signifies that the corresponding
block is locked for program and erase. A value of 0 in the lock register signifies that the corresponding
block is available to receive program and erase pulses.
The block numbering for Mid Address Space is given in the table below, and is different for Flash_A and
Flash_B.
The lock register is not writable once an interlock write is completed until FLASH_x_MCR[DONE] is set
at the completion of the requested operation. Likewise, the lock register is not writable if a high voltage
operation is suspended. MLOCK is also not writeable during UTest operations, when AIE is high.
Upon reset, information from the shadow block is loaded into the block registers. The LOCK bits may
be written as a register. Reset causes the bits to go back to their shadow block value. The default value
of the LOCK bits (assuming erased shadow location) is locked.
In the event that blocks are not present (due to configuration or total memory size), the LOCK bits
default to be locked, and are not writable. The reset value is always 1 (independent of the shadow
block), and register writes have no effect.
MLOCK is not writable unless LME is high.
MLOCK Bit
Flash_A Block
Flash_B Block
0
M0
M0
1
M1
none
Summary of Contents for PXR4030
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