Flash Memory Array and Control
Freescale Semiconductor
12-17
PXR40 Microcontroller Reference Manual, Rev. 1
12.2.2.5
Low/Mid Address Space Block Select Register (FLASH_x_LMSR)
The Low/Mid Address Space Block Select Register (FLASH_x_LMSR) provides a means to select blocks
to be operated on during erase.
The following field and bit descriptions fully define the FLASH_x_LMSR register (
FLASH_x_LMSR register functions, as shown in
.
14–15
SMLOCK
Secondary Mid Address Block Lock. This bit is an alternative method that may be used to lock the
Mid Address Space blocks from programs and erases. SMLOCK has the same description as
MLOCK in the FLASH_x_LMLR register. SMLOCK is not writable unless SLE is high.
16–21
Reserved
22–31
SLLOCK
Secondary Low Address Block Lock. This bit is an alternative method that may be used to lock the
Low Address Space blocks from programs and erases. SLLOCK has the same description as
LLOCK in the FLASH_x_LMLR register. SLLOCK is not writable unless SLE is high.
Offset 0x0010 / 0x4010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
0
0
MSEL
0 0 0 0 0 0
LSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-7. FLASH_x_LMSR Register
Table 12-9. FLASH_x_LMSR Field Descriptions
Field
Description
0–13
Reserved
14–15
MSEL
Mid Address Space Block Select. A value of 1 in the select register signifies that the block is selected for
erase. A value of 0 in the select register signifies that the block is not selected. The reset value for the
select registers is 0, or un-selected.
The blocks must be selected (or un-selected) before doing an erase interlock write as part of the erase
sequence. The select register is not writable once an interlock write is completed until
FLASH_x_MCR[DONE] is set at the completion of the requested operation, or if a high voltage operation
is suspended. MSEL is also not writeable during UTest operations, when AIE is high.
In the event that blocks are not present (due to configuration or total memory size), the corresponding
select bits default to un-selected, and are not writable. The reset value is always 0, and register writes
have no effect.
MSEL bits are mapped to block numbers in the same way as described for the MLOCK bits of the
FLASH_x_LMLR register.
Table 12-8. FLASH_x_SLMLR Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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