Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
13-10
Freescale Semiconductor
13.3.2.3
L1FINV0
This register is used to flush/invalidate cache sets/ways in the data cache. The SPR number for L1FINV0
is 1016 in decimal. The L1FINV0 register is shown below.
29
ICABT
Instruction Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted
prior to completion. This bit is set by hardware on an aborted condition, and will remain
set until cleared by software writing 0 to this bit location.
30
ICINV
Instruction Cache Invalidate
0 No cache invalidate
1 Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once
complete, this bit is reset to ‘0’. Writing a ‘1’ while an invalidation operation is in
progress will result in an undefined operation. Writing a ‘0’ to this bit while an
invalidation operation is in progress will be ignored. Cache invalidation operations
require approximately 134 cycles to complete. Invalidation occurs regardless of the
enable (ICE) value.
During cache invalidations, the parity check bits are written with a value dependent on
the ICEDT selection. ICEDT should be written with the desired value for subsequent
cache operation when ICINV is set to ‘1’ for proper operation of the cache.
31
ICE
Instruction Cache Enable
0 Cache is disabled
1 Cache is enabled
When disabled, cache lookups are not performed for instruction accesses.
Other L1CSR1 cache control operations are still available and are not affected by ICE.
1
These bits are not implemented and should be written with zero for future compatibility.
0
CW
A
Y
0
CSET
0
CCMD
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1016; Read/Write; Reset - 0x0
Figure 13-3. L1 Flush/Invalidate Register 0 (L1FINV0)
Table 13-3. L1FINV0 Field Descriptions
Field
Description
0–5
Reserved
1
for way extension
6–7
CWAY
Cache Way
Specifies the data cache way to be selected
8–19
Reserved
for set extension
20–26
CSET
Cache Set
Specifies the cache set to be selected
Table 13-2. L1CSR1 Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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