Memory Protection Unit (MPU)
16-10
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
identification field within the definition. Bus masters 4–7 are typically reserved for data movement
engines and their capabilities are limited to separate read and write permissions. For these fields, the bus
master number refers to the logical master number defined as the AHB
hmaster[3:0]
signal.
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
•
Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
•
Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
•
Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
The evaluation logic defines the processor access type based on multiple AHB signals: read or write as
specified by the
hwrite
signal and the low-order two bits of
hprot[1:0]
,
which identify a data reference
versus an instruction fetch and the operating mode (supervisor, user) of the requesting processor.
For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses
hwrite
to
determine if the access is a read or write. The
hprot[1:0]
signal is ignored for these masters.
Writes to this word clear the region descriptor’s valid bit. Because it is also expected that system software
may adjust only the access controls within a region descriptor (MPU_RGD
n
.Word2) as different tasks
execute, an alternate programming view of this 32-bit entity is provided. If only the access controls are
being updated, this operation should be performed by writing to MPU_RGDAAC
n
(alternate access
control
n
) as stores to these locations do not affect the descriptor’s valid bit.
Offset: MP 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
M6RE M6WE M5RE M5WE M4RE M4WE
0
0
0
0
0
0
0
0
W
Reset
(n=0)
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
Reset
(n>0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
M0PE
M0SM
M0UM
W
r
w
x
Reset
(n=0)
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Reset
(n>0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
to see the Master ID assignments.
Figure 16-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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