Error Correction Status Module (ECSM)
Freescale Semiconductor
17-15
PXR40 Microcontroller Reference Manual, Rev. 1
17.2.2.14 RAM ECC Master Number Register (ECSM_REMR)
The ECSM_REMR is an 8-bit register for capturing the XBAR bus master number of the last,
properly-enabled ECC event in the RAM memory. Depending on the state of the ECC configuration
register, an ECC event in the RAM causes the address, attributes, and data associated with the access to be
loaded into the ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT, and ECSM_REDR
registers and also the appropriate flag (RNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC master number register definition.
17.2.2.15 RAM ECC Attributes Register (ECSM_REAT)
The ECSM_REAT is an 8-bit register for capturing the XBAR bus master attributes of the last properly
enabled ECC event in the RAM memory. Depending on the state of the ECC configuration register, an
ECC event in the RAM causes the address, attributes, and data associated with the access to be loaded into
the ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT, and ECSM_REDR registers and also
the appropriate flag (RNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC attributes register definition.
Offset: ECSM_BAS 0x0066
Access: User read-only
0
1
2
3
4
5
6
7
R
0
0
0
0
REMR
W
Reset
0
0
0
0
U
1
1
U = undefined at reset
U
U
U
Figure 17-12. RAM ECC Master Number (ECSM_REMR) Register
Table 17-14. ECSM_REMR Field Descriptions
Field
Description
0–7
REMR
RAM ECC Master Number Register. Contains the XBAR bus master number of the faulting access of the last,
properly-enabled RAM ECC event.
Offset: ECSM_BAS 0x0067
Access: User read-only
0
1
2
3
4
5
6
7
R
WRITE
SIZE
PROTECTION
W
Reset
U
1
1
U = undefined at reset
U
U
U
U
U
U
U
Figure 17-13. RAM ECC Attributes (ECSM_REAT) Register
Summary of Contents for PXR4030
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