Introduction
Freescale Semiconductor
1-17
PXR40 Microcontroller Reference Manual, Rev. 1
multiplexing and selection logic (provides an interrupt request to the core that is higher priority
than any other interrupting source in the device)
1.2.20
Frequency-modulated PLL (FMPLL)
The FMPLL allows the user to generate high speed system clocks using a 4 MHz to 40 MHz crystal
oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation
of the system clock to reduce electromagnetic emissions peaks. The PLL multiplication factor and output
clock divider ratio are all software configurable. The PLL has the following major features:
•
Input clock frequency selectable in two ranges:
— From 4 MHz to 20 MHz
— From 8 MHz to 40 MHz (when PLLCFG2 pulled high)
•
Voltage controlled oscillator (VCO) range from 192 MHz to 680 MHz
•
Reduced frequency divider (RFD) for reduced frequency operation without requiring PLL relock
•
Three modes of operation:
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
•
Each of the three modes may be run with a crystal oscillator or an external clock reference
•
Programmable frequency modulation
1
— Modulation enabled/disabled through software
— Triangle wave modulation
— Programmable modulation depth
— Programmable modulation frequency dependent on reference frequency
•
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors
lock status to report loss of lock conditions
•
Clock quality module
— Optionally causes an interrupt request or system reset if the crystal clock frequency falls
outside a predefined range
— Optionally causes a system reset, or switches the system clock to the crystal clock and causes
an interrupt request, if the PLL output clock frequency falls outside a predefined range
•
Programmable interrupt request or system reset on loss of lock
•
Self-clocked mode (SCM) operation allows continued operation after failure of crystal clock
•
Configuration registers defined as an upwardly compatible superset of MPC5500 FMPLL registers
1. You must configure the FMPLL to ensure that the maximum specified system frequency is not exceeded when frequency
modulation is enabled.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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