FlexRay Communication Controller (FLEXRAY)
Freescale Semiconductor
22-41
PXR40 Microcontroller Reference Manual, Rev. 1
22.5.2.31 Sync Frame Counter Register (SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the controller will not
update the fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the controller will not update
the values SFODB and SFODA.
22.5.2.32 Sync Frame Table Offset Register (SFTOR)
This register defines the Flexray Memory related offset for sync frame tables. For more details, see
Section 22.6.12, Sync Frame ID and Sync Frame Deviation Tables
.
Base + 0x0040
Additional Reset: RUN Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SFEVB
SFEVA
SFODB
SFODA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-31. Sync Frame Counter Register (SFCNTR)
Table 22-37. SFCNTR Field Descriptions
Field
Description
SFEVB
Sync Frames Channel B, even cycle — protocol related variable: size of (
vsSyncIdListB
for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFEVB
Sync Frames Channel A, even cycle — protocol related variable: size of (
vsSyncIdListA
for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFODB
Sync Frames Channel B, odd cycle — protocol related variable: size of (
vsSyncIdListB
for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
SFODA
Sync Frames Channel A, odd cycle — protocol related variable: size of (
vsSyncIdListA
for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
Base + 0x0042
Write:
POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SFT_OFFSET[15:1]
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-32. Sync Frame Table Offset Register (SFTOR)
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
