FlexRay Communication Controller (FLEXRAY)
22-58
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22.5.2.55 Receive FIFO Depth and Size Register (RFDSR)
This register defines the structure of the selected FIFO, i.e. the number of entries and the size of each entry.
22.5.2.56 Receive FIFO A Read Index Register (RFARIR)
This register provides the message buffer header index of the next available FIFO A entry that the
application can read.
Table 22-64. RFSIR Field Descriptions
Field
Description
SIDX
A
SIDX
B
Start Index — This field defines the number of the message buffer header field of the first message buffer of the
selected FIFO. The controller uses the value of the SIDX field to determine the physical location of the receiver
FIFO’s first message buffer header field.
Base + 0x008A
Write:
POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FIFO_DEPTH
A
/FIFO_DEPTH
B
0
ENTRY_SIZE
A
/ENTRY_SIZE
B
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-56. Receive FIFO Depth and Size Register (RFDSR)
Table 22-65. RFDSR Field Descriptions
Field
Description
FIFO_DEPTH
A
FIFO_DEPTH
B
FIFO Depth — This field defines the depth of the selected FIFO, i.e. the number of entries.
ENTRY_SIZE
A
ENTRY_SIZE
B
Entry Size — This field defines the size of the frame data sections for the selected FIFO in 2 byte entities.
Base + 0x008C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
RDIDX
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-57. Receive FIFO A Read Index Register (RFARIR)
Table 22-66. RFARIR Field Descriptions
Field
Description
RDIDX
Read Index — This field provides the message buffer header index of the next available FIFO message buffer
that the application can read.
If the old style FIFO mode is configured (MCR.FIMD=0), the controller updates this index by 1 entry, when the
application writes to the FAFAIF flag in the
Global Interrupt Flag and Enable Register (GIFER)
If the new style FIFO mode is configured (MCR.FIMD=1), the controller updates this index by PCA entries, when
the application writes to the
Receive FIFO Fill Level and POP Count Register (RFFLPCR)
.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
