FlexRay Communication Controller (FLEXRAY)
22-124
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22.6.9.1
Overview
The two receive FIFOs implement the queued message buffer concept defined by the
Communications System Protocol Specification, Version 2.1 Rev A.
One FIFO is assigned to channel A,
the other FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in
Section 22.6.3.3, Receive FIFO.
The area in the
flexray memory for each of the two FIFOs is characterized by:
•
The FIFO system memory base address
•
The index of the first FIFO entry given by
Receive FIFO Start Index Register (RFSIR)
•
The number of FIFO entries and the length of each FIFO entry as given by
22.6.9.2
FIFO Configuration
The FIFOs can be configured for two different locations of the system memory base address via the FIFO
address mode bit FAM in the
Module Configuration Register (MCR)
22.6.9.2.1
Single System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 0. In this mode, the
location of the system memory base address for the FIFO buffers is
.
22.6.9.2.2
Dual System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 1. In this mode, the
location of the system memory base address for the FIFO buffers is
Receive FIFO System Memory Base
The FIFO control and configuration data are given in
Section 22.6.3.7, Receive FIFO Control and
The configuration of the FIFOs consists of two steps.
The first step is the allocation of the required amount of flexray memory for the FlexRay window. This
includes the allocation of the message buffer header area and the allocation of the message buffer data
fields. For more details see
Section 22.6.4, FlexRay Memory Layout.
The second step is the programming of the configuration data register while the PE is in
POC:config.
The following steps configure the layout of the FIFO.
•
Configure the FIFO update and address modes in
Module Configuration Register (MCR)
•
Configure the FIFO system memory base address
•
Configure the
Receive FIFO Start Index Register (RFSIR)
with the first message buffer header
index that belongs to the FIFO
•
Configure the
Receive FIFO Depth and Size Register (RFDSR)
•
Configure the
Receive FIFO Depth and Size Register (RFDSR)
•
Configure the FIFO Filters
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
