FlexRay Communication Controller (FLEXRAY)
Freescale Semiconductor
22-145
PXR40 Microcontroller Reference Manual, Rev. 1
22.6.20.1.2
FIFO Interrupts
The controller provides 2 FIFO interrupt sources.
Each of the 2 FIFO provides a Receive FIFO Almost Full Interrupt Flag. The controller sets the Receive
FIFO Almost Full Interrupt Flags (GIFER.FAFBIF, GIFER.FAFAIF) in the
if the corresponding Receive FIFO fill level exceeds the defined watermark.
22.6.20.1.3
Wakeup Interrupt
The controller provides one interrupt source related to the wakeup.
The controller sets the Wakeup Interrupt Flag GIFER.WUPIF when it has received a wakeup symbol on
the FlexRay bus. The controller generates an interrupt request if the interrupt enable bit GIFER.WUPIE is
asserted.
22.6.20.1.4
Protocol Interrupts
The controller provides 25 interrupt sources for protocol related events. For details, see
and
Protocol Interrupt Flag Register 1 (PIFR1)
. Each interrupt source has its own
interrupt enable bit.
22.6.20.1.5
CHI Error Interrupts
The controller provides 16 interrupt sources for CHI related error events. For details, see
. There is one common interrupt enable bit GIFER.CHIIE for all CHI error interrupt
sources.
22.6.20.2 Combined Interrupt Sources
Each combined interrupt source generates an interrupt request only when at least one of the interrupt
sources that is combined generates an interrupt request.
22.6.20.2.1
Receive Message Buffer Interrupt
The combined receive message buffer interrupt request RBIRQ is generated when at least one of the
individual receive message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit
GIFER.RBIE is set.
22.6.20.2.2
Transmit Message Buffer Interrupt
The combined transmit message buffer interrupt request TBIRQ is generated when at least one of the
individual transmit message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable
bit GIFER.TBIE is asserted.
22.6.20.2.3
Protocol Interrupt
The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol
interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
