Enhanced Modular Input/Output Subsystem (eMIOS200)
Freescale Semiconductor
23-41
PXR40 Microcontroller Reference Manual, Rev. 1
The A1 load signal is generated based on the detection of the internal counter reaching 0x00_0001 and has
the duration of one system clock cycle. During the load pulse, A1 still holds its previous value. It is updated
at the second system clock cycle only. Thus, A1 is updated with A2 value at the same time that the counter
(EMIOS_CCNTR[
n
]) is loaded with 0x00_0001. The load signal pulse has the duration of one system
clock period. If A2 is written within cycle (
n
), its value is available at A1 at the first clock of cycle (
n
+ 1)
and the new value is used for match at cycle (
n
+ 1). The update disable bits OU[
n
] of the EMIOS_OUDR
register can be used to control the update of this register, thus allowing the A1 register update to be delayed
for synchronization purposes.
Figure 23-36. MCB Mode A1 Register Update in Up Counter Mode
shows the A1 register update in up/down counter mode. Note that A2 can be written at any
time within cycle (
n
) in order to be used in cycle (
n
+ 1). Thus A1 receives this new value at the next cycle
boundary. The update disable bits (OU[
n
] in EMIOS_OUDR) can be used to disable the update of A1
register.
Figure 23-37. MCB Mode A1 Register Update in Up/Down Counter Mode
A1 Value
0x000008
0x000008
0x000001
Internal Counter
0x000004
0x000006
A2 Value
0x000008
0x000004
0x000006
0x000002
0x000004
0x000006
Write to A2
A1 Load Signal
8
4
6
Counter = A1
Time
Cycle n
Cycle n + 1
Cycle n + 2
A1 match
A1 match
A1 match
Write to A2
1
Prescaler Ratio = 2
EMIOS_CCNTR[n]
Time
Write to A2
A1 Match
A1 Match
Write to A2
0x000001
0x000005
0x000006
0x000005
A2 Value
A1 Value
0x000006
0x000005
Selected Counter = 2
A1 Load Signal
0x000006
0x000006
0x000006
Cycle n
Cycle n + 1
Cycle n + 2
Prescaler Ratio = 2
Summary of Contents for PXR4030
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