FlexCAN Module
Freescale Semiconductor
24-15
PXR40 Microcontroller Reference Manual, Rev. 1
3
HALT
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after initializing
the Message Buffers and Control Register. No reception or transmission is performed by FlexCAN before
this bit is cleared. While in Freeze Mode, the CPU has write access to the Error Counter Register, that is
otherwise read-only. Freeze Mode can not be entered while FlexCAN is in any of the low power modes.
See
Section 24.4.9.1, Freeze Mode,
for more information.
0 No Freeze Mode request.
1 Enters Freeze Mode if the FRZ bit is asserted.
4
NOT_RDY
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable Mode, Stop Mode or Freeze Mode. It is
negated once FlexCAN has exited these modes.
0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
1 FlexCAN module is either in Disable Mode, Stop Mode or Freeze Mode
5
Reserved
6
SOFT_RST
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped
registers. The following registers are reset: FLEXCAN_x_MCR (except the MDIS bit),
FLEXCAN_x_TIMER, FLEXCAN_x_ECR, FLEXCAN_x_ESR, FLEXCAN_x_IMASK1,
FLEXCAN_x_IMASK2, FLEXCAN_x_IFLAG1, FLEXCAN_x_IFLAG2. Configuration registers that control
the interface to the CAN bus are not affected by soft reset. The following registers are unaffected:
• FLEXCAN_x_CTRL
• RXIMR0–RXIMR63
• FLEXCAN_x_RXGMASK, FLEXCAN_x_RX14MASK, FLEXCAN_x_RX15MASK
• all Message Buffers
The SOFT_RST bit can be asserted directly by the CPU when it writes to the FLEXCAN_x_MCR Register,
but it is also asserted when global soft reset is requested at MCU level. Since soft reset is synchronous
and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully
propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is automatically
negated when reset completes. Therefore, software can poll this bit to know when the soft reset has
completed.
Soft reset cannot be applied while clocks are shut down in any of the low power modes. The module
should be first removed from low power mode, and then soft reset can be applied.
0 No reset request
1 Resets the registers marked as “affected by soft reset” in
7
FRZ_ACK
Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze
Mode request cannot be granted until current transmission or reception processes have finished.
Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually entered Freeze
Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN prescaler is running
again. If Freeze Mode is requested while FlexCAN is in any of the low power modes, then the FRZ_ACK
bit will only be set when the low power mode is exited. See
Section 24.4.9.1, Freeze Mode,
for more
information.
0 FlexCAN not in Freeze Mode, prescaler running
1 FlexCAN in Freeze Mode, prescaler stopped
Table 24-8. FLEXCAN_x_MCR Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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