Deserial Serial Peripheral Interface (DSPI)
25-50
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 25-29. DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8)
The master initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate
peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its
SOUT pin. After the
t
CSC
delay has elapsed, the master outputs the first edge of SCK. This is the edge used
by the master and slave devices to sample the first input data bit on their serial data input signals. At the
second edge of the SCK the master and slave devices place their second data bit on their serial data output
signals. For the rest of the frame the master and the slave sample their SIN pins on the odd-numbered clock
edges and changes the data on their SOUT pins on the even-numbered clock edges. After the last clock
edge occurs a delay of
t
ASC
is inserted before the master negates the PCS signals. A delay of t
DT
is inserted
before a new frame transfer can be initiated by the master.
25.4.7.2
Classic SPI Transfer Format (CPHA = 1)
This transfer format shown in
is used to communicate with peripheral SPI slave devices that
require the first SCK edge before the first data bit becomes available on the slave SOUT pin. In this format
the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and
sample the data on their SIN pins on the even-numbered SCK edges
t
CSC
SCK
Master and Slave
PCSx/SS
SCK
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
Master SOUT/
Master SIN/
t
DT
t
CSC
t
CSC
= PCS to SCK delay
t
DT
= Delay after Transfer (Minimum CS idle time)
(CPOL = 0)
(CPOL = 1)
t
ASC
Slave SIN
Slave SOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Sample
t
ASC
= After SCK delay
Summary of Contents for PXR4030
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