Decimation Filter
Freescale Semiconductor
28-19
PXR40 Microcontroller Reference Manual, Rev. 1
28.2.2.5
Decimation Filter Interface Input Buffer Register (DECFILT_x_IB)
The Input Buffer Register provides access to the Input buffer of the decimation filter when the filter is
receiving input data from the CPU/DMA (DECFILT_x_MCR[IO_SEL[1]] = 1). Writes to this register are
interpreted as requests to the Decimation Filter to process new sample data. Writes to this register when
DECFILT_x_MCR[IO_SEL[1]] = 0 have no effect.
Address: DECFILT_ 0x010
Access: User read/write
R
0
0
0
0
INTAG[3:0]
0
0
0
0
0
0
PRE
FILL
FLUSH
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
INPBUF[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-6. Decimation Filter Interface Input Buffer Register (DECFILT_x_IB)
Table 28-8. DECFILT_x_IB Field Descriptions
Field
Description
0–3
Reserved
4–7
INTAG
Decimation filter input tag bits —The INTAG[3:0] bit field is defined as a selector signal and it is used to identify
different destinations for the INBUF[15:0] data.
When the input data source is the CPU/DMA and the output destination is an eQADC, INTAG is used to address
the appropriate RFIFO in the eQADC block.
8–13
Reserved
14
PREFILL
Decimation Filter Prefill/Filter control bit—The PREFILL bit selects the Decimation Filter operation mode. For
more details, see
Section 28.3.4, Filter Prefill Control
0 Decimation Filter normal sample
1 Decimation Filter prefill sample
15
FLUSH
Decimation Filter Flush control bit—Assertion of the FLUSH bit initializes the Decimation Filter to a initial state,
as defined in
. This bit is self negated and it is cleared only when the data is
read and the flush is executed.
0 No flush request
1 Flush request
16–31
INPBUF
Input Buffer Data—The INPBUF[15:0] bit field carries the sample data to be filtered. This data buffer can be
written from the eQADC or by the CPU/DMA. See
Section 28.3.1, Decimation Filter Input
, for more details.
Summary of Contents for PXR4030
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