Decimation Filter
Freescale Semiconductor
28-21
PXR40 Microcontroller Reference Manual, Rev. 1
28.2.2.8
Decimation Filter TAPn Register (DECFILT_x_TAPn)
Table 28-10. DECFILT_x_COEFn Field Descriptions
Field
Description
0–31
COEFn
Coefficient n field—The COEFn[23:0] bit fields are the digital filter coefficients registers. The coefficients are
fractional signed values in two’s complement format, in the range (-1
coef < 1).
Note: Reads to this register are sign-extended, meaning the coefficient’s sign bit is copied to all 8 most
significant register bits.
Note: Writing to these fields when BSY=1 is not allowed.
Address: DECFILT_ 0x078–0x094
Access: User read only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
8{TAPn[23]}
TAPn[23:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TAPn[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-9. Decimation Filter TAPn Register (DECFILT_x_TAPn)
Table 28-11. DECFILT_x_TAPn Field Descriptions
Field
Description
0–31
TAPn
TAPn Register—The read-only TAPn[23:0] bit fields shows the contents of the digital filter tap registers, as
fractional signed values in two’s complement format, in the range (-1
coef < 1). The tap registers hold the input
data delay line (Xn, Xn-1,......,Xn-7 for 8th order FIR).
Note: Reads to this register are sign-extended, meaning the coefficient’s sign bit is copied to all 8 most
significant register bits.
Note: The content of these registers is meaningless when BSY=1.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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